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2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)最新文献

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A study of interferences inside an RF switch array in 45nm SOI CMOS 45nm SOI CMOS射频开关阵列内部干扰研究
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309266
Chenkun Wang, Fei Lu, Qi Chen, Feilong Zhang, Cheng Li, Dawn Wang, Albert Z. H. Wang
{"title":"A study of interferences inside an RF switch array in 45nm SOI CMOS","authors":"Chenkun Wang, Fei Lu, Qi Chen, Feilong Zhang, Cheng Li, Dawn Wang, Albert Z. H. Wang","doi":"10.1109/S3S.2017.8309266","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309266","url":null,"abstract":"This paper presents a study of interferences inside an RF switch array, aiming to understand the design influences on interference characteristics. The 2×2 single-pole double/triple-throw (SP2T/SP3T) Tx/Rx band switch array, featuring a series-shunt topology with gate resistance and feed-forward capacitance (FFC) and covering low (699–894MHz) and high (1710–2155MHz) bands, was designed and fabricated in a 45nm SOI CMOS. The inter-band and inner-band interferences were characterized, which reveals that existing noise isolation techniques, e.g., substrate isolation and layout floor planning, are insufficient for interference reduction. It therefore calls for novel in-die interference elimination techniques.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114911552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
FinFETs on insulator with silicided source/drain 硅化源极/漏极绝缘体上的finfet
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309228
Huilong Zhu, Jun Luo, Qingzhu Zhang, H. Yin, H. Zhong, Chao Zhao
{"title":"FinFETs on insulator with silicided source/drain","authors":"Huilong Zhu, Jun Luo, Qingzhu Zhang, H. Yin, H. Zhong, Chao Zhao","doi":"10.1109/S3S.2017.8309228","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309228","url":null,"abstract":"In this paper, some new developments of SOI and FOI (fin-on-insulator) FinFETs with conventional silicide S/D and Schottky barrier S/D are summarized. It is observed that large junction leakages occur for bulk FinFETs with conventional silicide S/D. By forming Ni(Pt)Si (5% Pt) silicide with conventional silicide process, parasitic resistances of FOI FinFETs are dramatically reduced without increasing of leakage currents and then device performance are increased significantly. An additional 50% performance enhancement is achieved for the FOI FinFETs with Schottky barrier S/D. The good controls of short channel effects and channel leakage are also obtained for FinFETs on insulator. High-k metal gate is used for the FinFETs.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133545364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A partitioning-free methodology for optimized gate-level monolithic 3D designs 一种优化栅极级单片三维设计的无分割方法
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309221
O. Billoint, M. Brocard, S. Thuries, G. Berhault, H. Sarhan
{"title":"A partitioning-free methodology for optimized gate-level monolithic 3D designs","authors":"O. Billoint, M. Brocard, S. Thuries, G. Berhault, H. Sarhan","doi":"10.1109/S3S.2017.8309221","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309221","url":null,"abstract":"This paper presents a partitioning-free algorithm that transforms a 2D design into a gate-level Monolithic 3D one, reducing design footprint by 50%, total wire length by 15% and net switching power by at least 30% around iso-performance (considered with a 5% margin) for all the benchmark blocks (openMSP, FFT, LDPC and 128-bits AES) in 28nm technology.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116895180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High-density SRAM voltage scaling enabled by inserted-oxide FinFET technology 通过插入氧化物FinFET技术实现高密度SRAM电压缩放
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309217
Yi-Ting Wu, M. Chiang, Jone F. Chen, F. Ding, D. Connelly, T. Liu
{"title":"High-density SRAM voltage scaling enabled by inserted-oxide FinFET technology","authors":"Yi-Ting Wu, M. Chiang, Jone F. Chen, F. Ding, D. Connelly, T. Liu","doi":"10.1109/S3S.2017.8309217","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309217","url":null,"abstract":"A scheme to precisely adjust the drive strength of an inserted-oxide FinFET (iFinFET), to enhance the manufacturing yield of a minimally sized six-transistor (6-T) SRAM cell, is proposed. Specifically, the top nanowire (NW) channel in an iFinFET can be made to be essentially non-conducting by ion implantation to increase its threshold voltage, and the position of the inserted-oxide layer can be optimized for maximum cell yield at low operating voltage. Via three-dimensional (3-D) device simulations and a calibrated compact model, this scheme is projected to lower the minimum operating voltage (Vmin) of a minimally sized 6-T SRAM cell.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132912323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Enhanced silicon-on-insulator platform enabling new structures and applications 增强型绝缘体上硅平台，支持新结构和应用
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308739
A. Haapalinna, T. Aalto
{"title":"Enhanced silicon-on-insulator platform enabling new structures and applications","authors":"A. Haapalinna, T. Aalto","doi":"10.1109/S3S.2017.8308739","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308739","url":null,"abstract":"Performance expectations for microelectromechanical systems (MEMS), the central building blocks of smart systems, are increasing rapidly. The rapidly growing IoT industry sets completely new demands, while existing industries such as automotive sensing is rapidly moving to a completely new requirements levels with autonomous driving (ADAS systems). Advanced MEMS devices are increasingly based on single crystal silicon, enabling uncompromised, high performance mechanical operation of the device. Efficient, repeatable mass production is achieved by utilizing state-of-the-art MEMS processing technology based on thick-film bonded Silicon-On-Insulator wafers (BSOI) starting material. Continuous device shrinking and requirements for unprecedented performance for high end sensors are driving requirements for SOI wafer specifications to a level at which traditional planarization technologies like chemical mechanical polishing (CMP) are stretched to their limits. At the same time, emerging applications are posing new challenges, requiring substrates with specifications that simply cannot be met with the traditional production technology.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134583786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Improving noise and linearity of CMOS wideband inductorless balun LNAs for 10-GHz software-defined radios in 28nm FDSOI 改善用于28nm FDSOI中10ghz软件定义无线电的CMOS宽带无电感平衡lna的噪声和线性度
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309267
C. Gimeno, François Stas, G. de Streel, D. Bol, D. Flandre
{"title":"Improving noise and linearity of CMOS wideband inductorless balun LNAs for 10-GHz software-defined radios in 28nm FDSOI","authors":"C. Gimeno, François Stas, G. de Streel, D. Bol, D. Flandre","doi":"10.1109/S3S.2017.8309267","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309267","url":null,"abstract":"This paper presents the analysis and optimization of inductorless balun low-noise amplifiers (LNA) in a 28-nm fully-depleted SOI CMOS technology for wideband universal software-defined radio transceivers by means of an algorithm that optimizes the main figures of merit. An optimum combination of two techniques is provided leading to a new topology that overcomes the main tradeoffs of the previous circuits improving both linearity and noise with competitive bandwidth (BW), gain and power. Post-layout simulations show a BW of 10 GHz, a gain of 17 dB, an IIP3 of 7.4 dBm, and a NF of 3.4 dB with only 2.5 mW power consumption from a 1-V supply.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131735013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI 28nm FD-SOI中低压双模逻辑的能量延迟权衡
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309250
R. Taco, I. Levi, M. Lanuzza, A. Fish
{"title":"Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI","authors":"R. Taco, I. Levi, M. Lanuzza, A. Fish","doi":"10.1109/S3S.2017.8309250","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309250","url":null,"abstract":"In this paper, the Dual Mode Logic (DML) technique is evaluated on a low-voltage 16-bit Carry Skip Adder in 28 nm UTBB FD-SOI technology. By combining the operating characteristics of the DML and the unique features of the technology, energy/speed efficient low-voltage adder designs can be defined. More precisely, it is demonstrated that, the capability of the DML design to switch on-the-fly between static and dynamic modes of operation leads to an improvement of more than 20% in terms of energy-delay product (EDP) in comparison to the conventional CMOS design. Moreover, the high efficiency of back plane biasing in the adopted technology allows very fine tuning of energy-delay performances of a DML design, thus emphasizing its intrinsic versatility.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130297015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Die-level processing for 3-D monolithic integration of piezoelectric MEMS on CMOS 压电MEMS在CMOS上三维单片集成的模级加工
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309207
Aida R. Colón-Berríos, H. Edrees, Daniel de Godoy, P. Kinget, I. Kymissis
{"title":"Die-level processing for 3-D monolithic integration of piezoelectric MEMS on CMOS","authors":"Aida R. Colón-Berríos, H. Edrees, Daniel de Godoy, P. Kinget, I. Kymissis","doi":"10.1109/S3S.2017.8309207","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309207","url":null,"abstract":"SMRs and FBARs allow for a wide variety of applications such as IR and mass sensors, RF filters, and signal generators. By integrating devices directly on CMOS, bonding and attachment parasitics can be eliminated, permitting the optimization of the design for each application. Using full wafers in a research environment is not cost-effective and developing a die process that allows the use of MPWs is of great benefit for research environments. In this work, we demonstrate several of the techniques that allow for 3D integration using small dies, and show the value of these techniques for piezoelectric MEMS structures.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124408224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
3D technologies for analog/RF applications 用于模拟/射频应用的3D技术
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308746
A. Vandooren, B. Parvais, L. Witters, A. Walke, A. Vais, C. Merckling, D. Lin, N. Waldron, P. Wambacq, D. Mocuta, N. Collaert
{"title":"3D technologies for analog/RF applications","authors":"A. Vandooren, B. Parvais, L. Witters, A. Walke, A. Vais, C. Merckling, D. Lin, N. Waldron, P. Wambacq, D. Mocuta, N. Collaert","doi":"10.1109/S3S.2017.8308746","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308746","url":null,"abstract":"In this work, we will review possible technology options for next generation wireless communication. Next to the introduction of specific device architectures and materials, dissimilar from standard Si CMOS, the challenge will lie in the co-integration of these non-Si technologies with CMOS to enable power efficient systems with high performance, in this case high speed and output power, and reduced form factor. Next to monolithic integration, sequential 3D, currently been investigated for LOGIC density scaling, can be one of the enablers, allowing to combine technologies with very different needs at a finer grain and thus higher density than traditional 3D-SOC and 3D-IC technologies.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128483914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
1μm Pitch direct hybrid bonding with <300nm wafer-to-wafer overlay accuracy 1μm间距直接杂化键合，晶圆间覆盖精度<300nm
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309213
A. Jouve, V. Balan, N. Bresson, C. Euvrard-Colnat, F. Fournel, Y. Exbrayat, G. Mauguen, M. A. Sater, C. Beitia, L. Arnaud, S. Chéramy, S. Lhostis, A. Farcy, S. Guillaumet, S. Mermoz
{"title":"1μm Pitch direct hybrid bonding with <300nm wafer-to-wafer overlay accuracy","authors":"A. Jouve, V. Balan, N. Bresson, C. Euvrard-Colnat, F. Fournel, Y. Exbrayat, G. Mauguen, M. A. Sater, C. Beitia, L. Arnaud, S. Chéramy, S. Lhostis, A. Farcy, S. Guillaumet, S. Mermoz","doi":"10.1109/S3S.2017.8309213","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309213","url":null,"abstract":"Copper/oxide hybrid bonding process has been extensively studied these past years as a key enabler for 3D high density application with top and bottom tier interconnection pitch below 10μm. Since 2015 hybrid bonding process robustness has been confirmed on complete electrical test vehicles [1,2] as well as commercial products [3] integrating copper to copper interconnection pitchs close to 6μm. To our knowledge, no results have been shown today demonstrating sub-1.5μm pitch copper hybrid bonding feasibility.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123721356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
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