1μm间距直接杂化键合，晶圆间覆盖精度<300nm

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI:10.1109/S3S.2017.8309213

A. Jouve, V. Balan, N. Bresson, C. Euvrard-Colnat, F. Fournel, Y. Exbrayat, G. Mauguen, M. A. Sater, C. Beitia, L. Arnaud, S. Chéramy, S. Lhostis, A. Farcy, S. Guillaumet, S. Mermoz

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引用次数: 29

摘要

在过去的几年里，铜/氧化物杂化键合工艺作为顶层和底层互连间距小于10μm的3D高密度应用的关键推动因素得到了广泛的研究。自2015年以来，混合键合工艺的稳健性已在完整的电动测试车[1,2]以及铜对铜互连间距接近6μm的商业产品[3]上得到证实。据我们所知，目前还没有结果表明低于1.5μm间距的铜杂化键合的可行性。

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1μm Pitch direct hybrid bonding with <300nm wafer-to-wafer overlay accuracy

Copper/oxide hybrid bonding process has been extensively studied these past years as a key enabler for 3D high density application with top and bottom tier interconnection pitch below 10μm. Since 2015 hybrid bonding process robustness has been confirmed on complete electrical test vehicles [1,2] as well as commercial products [3] integrating copper to copper interconnection pitchs close to 6μm. To our knowledge, no results have been shown today demonstrating sub-1.5μm pitch copper hybrid bonding feasibility.

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2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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