发布求助
文献互助 智能选刊 最新文献

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)最新文献

筛选
英文 中文
Analog circuits for mixed-signal neuromorphic computing architectures in 28 nm FD-SOI technology 28nm FD-SOI技术混合信号神经形态计算架构模拟电路
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-19 DOI: 10.1109/S3S.2017.8309203
Ning Qiao, G. Indiveri
{"title":"Analog circuits for mixed-signal neuromorphic computing architectures in 28 nm FD-SOI technology","authors":"Ning Qiao, G. Indiveri","doi":"10.1109/S3S.2017.8309203","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309203","url":null,"abstract":"Developing mixed-signal analog-digital neuromorphic circuits in advanced scaled processes poses significant design challenges. We present compact and energy efficient sub-threshold analog synapse and neuron circuits, optimized for a 28 nm FD-SOI process, to implement massively parallel large-scale neuromorphic computing systems. We describe the techniques used for maximizing density with mixed-mode analog/digital synaptic weight configurations, and the methods adopted for minimizing the effect of channel leakage current, in order to implement efficient analog computation based on pA-nA small currents. We present circuit simulation results, based on a new chip that has been recently taped out, to demonstrate how the circuits can be useful for both low-frequency operation in systems that need to interact with the environment in real-time, and for high-frequency operation for fast data processing in different types of spiking neural network architectures.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130764187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
New method for individual electrical characterization of stacked SOI nanowire MOSFETs 叠置SOI纳米线mosfet个别电特性的新方法
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-16 DOI: 10.1109/S3S.2017.8309237
B. C. Paz, M. Cassé, S. Barraud, G. Reimbold, M. Vinet, O. Faynot, M. Pavanello
{"title":"New method for individual electrical characterization of stacked SOI nanowire MOSFETs","authors":"B. C. Paz, M. Cassé, S. Barraud, G. Reimbold, M. Vinet, O. Faynot, M. Pavanello","doi":"10.1109/S3S.2017.8309237","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309237","url":null,"abstract":"A new systematic procedure to separate the electrical characteristics of advanced stacked nanowires (NWs) with emphasis on mobility extraction is presented. The proposed method is based on I-V measurements varying the back gate bias (VB) and consists of three basic main steps, accounting for VB influence on transport parameters. Lower mobility was obtained for the top GAA NW in comparison to bottom Q-NW. Temperature dependence of carrier mobility is also studied through the proposed method up to 150°C.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122606500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design methodology with body bias: From circuit to engineering 具有身体偏差的设计方法论:从电路到工程
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-16 DOI: 10.1109/S3S.2017.8309212
R. Gomez, C. Dutto, V. Huard, S. Clerc, E. Bano, P. Flatresse
{"title":"Design methodology with body bias: From circuit to engineering","authors":"R. Gomez, C. Dutto, V. Huard, S. Clerc, E. Bano, P. Flatresse","doi":"10.1109/S3S.2017.8309212","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309212","url":null,"abstract":"In this paper, a built-in Body Bias design methodology is proposed and implemented in two different contexts: the automotive industry and the IoT paradigm. As opposed to the traditional design strategy, the proposed methodology incorporates Body Bias in all design stages, from synthesis to engineering. Measurements performed in a leakage-driven ADAS product and a dual core application processor in 28nm UTBB-FDSOI technology confirm the effectiveness of the proposed methodology, achieving a 30% reduction in static power, 25% in dynamic power, 15% yield recovery, and a 4X frequency and 2X leakage spread reduction.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131597611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An improved mobility model for FDSOI TriGate and other multi-gate Nanowire MOSFETs down to nanometer-scaled dimensions 一种改进的FDSOI三门和其他多栅极纳米线mosfet的迁移率模型，可降至纳米尺度
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-16 DOI: 10.1109/S3S.2017.8309241
M. Cassé, J. Pelloux-Prayer, Z. Zeng, Y. Niquet, F. Triozon, S. Barraud, G. Reimbold
{"title":"An improved mobility model for FDSOI TriGate and other multi-gate Nanowire MOSFETs down to nanometer-scaled dimensions","authors":"M. Cassé, J. Pelloux-Prayer, Z. Zeng, Y. Niquet, F. Triozon, S. Barraud, G. Reimbold","doi":"10.1109/S3S.2017.8309241","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309241","url":null,"abstract":"We hereby present the experimental validation of a semi-analytical model for the size-dependent carrier mobility in FDSOI TriGate Nanowire transistors. The model is based on simple interpolation between a square narrow Si NW and wide FDSOI or vertical Double Gate (DG) limiting cases. We demonstrate its suitability to NMOS and PMOS devices with various H and W dimensions, as well as for different channel orientations. This model brings significant improvement to the simpler facets model, and evidences the contribution of corner areas.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130646929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A subthreshold 30pJ/bit self-timed ring based true random number generator for Internet of everything 面向万物互联的基于亚阈值30pJ/bit自定时环的真随机数发生器
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-16 DOI: 10.1109/S3S.2017.8308744
Mathieu Coustans, C. Terrier, T. Eberhardt, Stephanie Salgado, A. Cherkaoui, L. Fesquet
{"title":"A subthreshold 30pJ/bit self-timed ring based true random number generator for Internet of everything","authors":"Mathieu Coustans, C. Terrier, T. Eberhardt, Stephanie Salgado, A. Cherkaoui, L. Fesquet","doi":"10.1109/S3S.2017.8308744","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308744","url":null,"abstract":"This paper presents a true random-number generator that exploits the subthreshold properties of jitter of events propagating in a self-timed ring, and jitter of events propagating in an inverter-based ring oscillator. The design was implemented in a 180nm CMOS flash process. Devices provide high-quality random bit sequences passing FIPS 140-2 and NIST SP 800-22 statistical tests which guaranty a uniform distribution and unpredictability guarantee by a physics-based entropy source.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127867939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Cost projections and benefits for transistor-level 3-D integration with stacked nanowires 利用堆叠奈米线进行电晶体级3-D整合的成本预测与效益
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309235
Naveen Kumar Macha, Mostafizur Rahman
{"title":"Cost projections and benefits for transistor-level 3-D integration with stacked nanowires","authors":"Naveen Kumar Macha, Mostafizur Rahman","doi":"10.1109/S3S.2017.8309235","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309235","url":null,"abstract":"To continue scaling beyond 2-D CMOS with 3-D integration, any new 3-D IC technology has to be comparable or better than 2-D CMOS in terms of scalability, enhanced functionality, density, power, performance, cost, and reliability. Transistor-level 3-D integration carries the most potential in this regard. Recently, we proposed a stacked horizontal nanowire based transistor-level 3-D integration approach, called SN3D [1][2][3] that solves scaling challenges and achieves tremendous benefits with respect to 2-D CMOS while keeping manageable thermal profile. In this paper, we present the cost analysis of SN3D and show comparison with 2-D CMOS (2D), conventional TSV based 3-D (T3D) and Monolithic 3-D integrations (M3D). In our cost model, we capture the implications of manufacturing, circuit density, interconnects, bonding and heat in determining die cost, and evaluate how cost scales as transistor count increases. Since SN3D is a new 3-D IC fabric, based on our proposed manufacturing pathway[1] we assumed complexity of fabrication steps as proportionality constants in our cost estimation model. Our analysis revealed 86%, 72% and 74% reduction in area; 55%, 43% and 43% reduction in interconnects distribution and total interconnect length for SN3D, which largely contributed to 70%, 67% and 68% reduction in cost in comparison to 2D, T3D and M3D respectively.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115539198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Machine intelligence through 3D waferscale integration 机器智能通过3D晶圆级集成
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309198
Arvind Kumar, W. Wilcke
{"title":"Machine intelligence through 3D waferscale integration","authors":"Arvind Kumar, W. Wilcke","doi":"10.1109/S3S.2017.8309198","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309198","url":null,"abstract":"Bringing computing systems to the stage of Machine Intelligence will require a massive scaling in processing, memory, and interconnectivity, and thus a major change in how electronic systems are designed. Long overlooked because of its unsuitability for the exacting demands of enterprise computing, 3D waferscale integration offers a promising scaling path, due in large part to the fault-tolerant nature of many cognitive algorithms. This work explores this scaling path in greater detail, invoking a simple model of brain connectivity to examine the potential for 3D waferscale integration to meet the demanding interconnectivity requirements of Machine Intelligence.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122770582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Physical and circuit modeling of HfO2 based ferroelectric memories and devices 基于HfO2的铁电存储器和器件的物理和电路建模
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308732
M. Pešić, V. Di Lecce, M. Hoffmann, H. Mulaosmanovic, B. Max, U. Schroeder, S. Slesazeck, L. Larcher, T. Mikolajick
{"title":"Physical and circuit modeling of HfO2 based ferroelectric memories and devices","authors":"M. Pešić, V. Di Lecce, M. Hoffmann, H. Mulaosmanovic, B. Max, U. Schroeder, S. Slesazeck, L. Larcher, T. Mikolajick","doi":"10.1109/S3S.2017.8308732","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308732","url":null,"abstract":"The discovery of ferroelectric properties in polycrystalline HfO2 has revived the interest in ferroelectric (FE) memories, which shows scaling feasibility allowing targeting high-density storage applications. In order to provide engineering guidelines for FE memory devices it is crucial to establish a correlation between the electrical device performances and the underlying physical mechanisms. In this work, we will discuss physical and circuit modeling approaches for FE memories connecting the FE HfO2 materials properties to the electrical performances of memory cells, artificial synapse for neuromorphic and in memory computing applications.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114408419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Double-gate Si junction-less n-type transistor for high performance Cu-BEOL compatible applications using 3D sequential integration 双栅无硅结n型晶体管，用于使用3D顺序集成的高性能Cu-BEOL兼容应用
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309234
A. Vandooren, L. Witters, E. Vecchio, E. Kunnen, G. Hellings, L. Peng, F. Inoue, W. Li, N. Waldron, D. Mocuta, N. Collaert
{"title":"Double-gate Si junction-less n-type transistor for high performance Cu-BEOL compatible applications using 3D sequential integration","authors":"A. Vandooren, L. Witters, E. Vecchio, E. Kunnen, G. Hellings, L. Peng, F. Inoue, W. Li, N. Waldron, D. Mocuta, N. Collaert","doi":"10.1109/S3S.2017.8309234","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309234","url":null,"abstract":"We are proposing a double gate junction-less device with a processing temperature compatible with state-of-the-art dense low k dielectric back-end of line copper process. The thermal stability of the back-end of line process was studied, showing no degradation for an anneal temperature up to 500°C 1h. Using wafer bonding, a crystalline silicon layer can be transferred onto a carrier wafer followed by top device processing at low temperature with a gate first approach as well as direct W contacts with Ti/TiN barrier layer. To avoid dopant activation using high temperature anneal (spike), junction-less devices are used, where the uniform channel dopant implantation and activation can be done prior to the layer transfer.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129735465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Vertically-composed fine-grained 3D CMOS 垂直组成的细粒度3D CMOS
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309233
Mingyu Li, Jiajun Shi, Mostafizur Rahman, S. Khasanvis, Sachin Bhat, C. A. Moritz
{"title":"Vertically-composed fine-grained 3D CMOS","authors":"Mingyu Li, Jiajun Shi, Mostafizur Rahman, S. Khasanvis, Sachin Bhat, C. A. Moritz","doi":"10.1109/S3S.2017.8309233","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309233","url":null,"abstract":"Parallel and monolithic 3D integration directions realize 3D integrated circuits (ICs) by utilizing layer-by-layer implementations. In contrast, vertically composed 3D CMOS has eluded us likely due to the seemingly insurmountable CMOS circuit style connectivity requirement in 3D. In this paper, we describe Skybridge-3D-CMOS (S3DC), an IC fabric that shows for the first time a pathway to achieve fine-grained static CMOS circuit implementations leveraging the vertical direction. It employs a new fabric assembly scheme based on pre-doped vertical nanowire bundles and implements CMOS circuits in and across nanowires. It utilizes innovative connectivity features to realize CMOS connectivity in 3D. Evaluation results, for the implemented benchmarks, show 72%–77% reductions in power consumption, 13X-16X increases in density, and 2% loss to 9% benefit in best operating frequencies compared with the state-of-art transistor-level monolithic 3D technology.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114221644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信