垂直组成的细粒度3D CMOS

Mingyu Li, Jiajun Shi, Mostafizur Rahman, S. Khasanvis, Sachin Bhat, C. A. Moritz
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引用次数: 0

摘要

并行和单片三维集成方向采用逐层实现的方式实现三维集成电路。相比之下,垂直组合的3D CMOS可能由于在3D中似乎无法克服的CMOS电路风格连接要求而避开了我们。在本文中,我们描述了Skybridge-3D-CMOS (S3DC),这是一种IC结构,首次展示了利用垂直方向实现细粒度静态CMOS电路实现的途径。它采用了一种基于预掺杂垂直纳米线束的新型织物组装方案,并在纳米线内和纳米线间实现了CMOS电路。它利用创新的连接功能来实现3D的CMOS连接。对于已实施的基准测试,评估结果显示,与最先进的晶体管级单片3D技术相比,功耗降低72%-77%,密度增加13X-16X,最佳工作频率损失减少2%至9%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Vertically-composed fine-grained 3D CMOS
Parallel and monolithic 3D integration directions realize 3D integrated circuits (ICs) by utilizing layer-by-layer implementations. In contrast, vertically composed 3D CMOS has eluded us likely due to the seemingly insurmountable CMOS circuit style connectivity requirement in 3D. In this paper, we describe Skybridge-3D-CMOS (S3DC), an IC fabric that shows for the first time a pathway to achieve fine-grained static CMOS circuit implementations leveraging the vertical direction. It employs a new fabric assembly scheme based on pre-doped vertical nanowire bundles and implements CMOS circuits in and across nanowires. It utilizes innovative connectivity features to realize CMOS connectivity in 3D. Evaluation results, for the implemented benchmarks, show 72%–77% reductions in power consumption, 13X-16X increases in density, and 2% loss to 9% benefit in best operating frequencies compared with the state-of-art transistor-level monolithic 3D technology.
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