An improved mobility model for FDSOI TriGate and other multi-gate Nanowire MOSFETs down to nanometer-scaled dimensions

Abstract

We hereby present the experimental validation of a semi-analytical model for the size-dependent carrier mobility in FDSOI TriGate Nanowire transistors. The model is based on simple interpolation between a square narrow Si NW and wide FDSOI or vertical Double Gate (DG) limiting cases. We demonstrate its suitability to NMOS and PMOS devices with various H and W dimensions, as well as for different channel orientations. This model brings significant improvement to the simpler facets model, and evidences the contribution of corner areas.