M. Cassé, J. Pelloux-Prayer, Z. Zeng, Y. Niquet, F. Triozon, S. Barraud, G. Reimbold
{"title":"一种改进的FDSOI三门和其他多栅极纳米线mosfet的迁移率模型,可降至纳米尺度","authors":"M. Cassé, J. Pelloux-Prayer, Z. Zeng, Y. Niquet, F. Triozon, S. Barraud, G. Reimbold","doi":"10.1109/S3S.2017.8309241","DOIUrl":null,"url":null,"abstract":"We hereby present the experimental validation of a semi-analytical model for the size-dependent carrier mobility in FDSOI TriGate Nanowire transistors. The model is based on simple interpolation between a square narrow Si NW and wide FDSOI or vertical Double Gate (DG) limiting cases. We demonstrate its suitability to NMOS and PMOS devices with various H and W dimensions, as well as for different channel orientations. This model brings significant improvement to the simpler facets model, and evidences the contribution of corner areas.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An improved mobility model for FDSOI TriGate and other multi-gate Nanowire MOSFETs down to nanometer-scaled dimensions\",\"authors\":\"M. Cassé, J. Pelloux-Prayer, Z. Zeng, Y. Niquet, F. Triozon, S. Barraud, G. Reimbold\",\"doi\":\"10.1109/S3S.2017.8309241\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We hereby present the experimental validation of a semi-analytical model for the size-dependent carrier mobility in FDSOI TriGate Nanowire transistors. The model is based on simple interpolation between a square narrow Si NW and wide FDSOI or vertical Double Gate (DG) limiting cases. We demonstrate its suitability to NMOS and PMOS devices with various H and W dimensions, as well as for different channel orientations. This model brings significant improvement to the simpler facets model, and evidences the contribution of corner areas.\",\"PeriodicalId\":333587,\"journal\":{\"name\":\"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-10-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/S3S.2017.8309241\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/S3S.2017.8309241","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An improved mobility model for FDSOI TriGate and other multi-gate Nanowire MOSFETs down to nanometer-scaled dimensions
We hereby present the experimental validation of a semi-analytical model for the size-dependent carrier mobility in FDSOI TriGate Nanowire transistors. The model is based on simple interpolation between a square narrow Si NW and wide FDSOI or vertical Double Gate (DG) limiting cases. We demonstrate its suitability to NMOS and PMOS devices with various H and W dimensions, as well as for different channel orientations. This model brings significant improvement to the simpler facets model, and evidences the contribution of corner areas.