发布求助
文献互助 智能选刊 最新文献

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)最新文献

筛选
英文 中文
Hybrid silicon CMOS-carbon nanotube physically unclonable functions 杂化硅cmos -碳纳米管物理上不可克隆的功能
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309206
D. Armstrong, B. Nasri, R. Karri, D. Shahrjerdi
{"title":"Hybrid silicon CMOS-carbon nanotube physically unclonable functions","authors":"D. Armstrong, B. Nasri, R. Karri, D. Shahrjerdi","doi":"10.1109/S3S.2017.8309206","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309206","url":null,"abstract":"Physically unclonable functions (PUFs) are used to uniquely identify electronic devices. Here, we introduce a hybrid silicon CMOS-nanotube PUF circuit that uses the variations of nanotube transistors to generate a random response. An analog silicon circuit subsequently converts the nanotube response to zero or one bits. We fabricate an array of nanotube transistors to study and model their device variability. The behavior of the hybrid CMOS-nanotube PUF is then simulated. The parameters of the analog circuit are tuned to achieve the desired normalized Hamming inter-distance of 0.5. The co-design of the nanotube array and the silicon CMOS is an attractive feature for increasing the immunity of the hybrid PUF against an unauthorized duplication. The heterogeneous integration of nanotubes with silicon CMOS offers a new strategy for realizing security tokens that are strong, low-cost, and reliable.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114716484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analog performance of self-cascode SOI nanowires nMOSFETs aiming at low-power applications 面向低功耗应用的自级联编码SOI纳米线nmosfet模拟性能
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309218
R. Assalti, M. de Souza, M. Cassé, S. Barraud, G. Reimbold, M. Vinet, O. Faynot
{"title":"Analog performance of self-cascode SOI nanowires nMOSFETs aiming at low-power applications","authors":"R. Assalti, M. de Souza, M. Cassé, S. Barraud, G. Reimbold, M. Vinet, O. Faynot","doi":"10.1109/S3S.2017.8309218","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309218","url":null,"abstract":"This paper experimentally explores the analog performance of Self-Cascode structures composed by SOI Nanowire nMOSFETs operating near the subthreshold regime. The composite structure uses transistors with distinct channel widths, biased in several back-gate voltages, to promote different threshold voltages.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125810747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High-performance spiking neural net accelerators for embedded computer vision applications 用于嵌入式计算机视觉应用的高性能峰值神经网络加速器
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309204
J. K. Kim, Phil C. Knag, Thomas Chen, Chester Liu, Ching-En Lee, Zhengya Zhang
{"title":"High-performance spiking neural net accelerators for embedded computer vision applications","authors":"J. K. Kim, Phil C. Knag, Thomas Chen, Chester Liu, Ching-En Lee, Zhengya Zhang","doi":"10.1109/S3S.2017.8309204","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309204","url":null,"abstract":"One key component in computer vision algorithms involves developing and identifying relevant features from raw data. In this work, we designed spiking recurrent neural net accelerators to implement a class of unsupervised machine learning algorithms known as sparse coding. The accelerators perform fast unsupervised learning of features, and extract sparse representations of inputs for low-power classification. Taking advantage of high sparsity, spiking neurons, and error tolerance, the compact accelerator chips are capable of processing images at several hundred megapixels per second, while dissipating less than 10 mW. The accelerators can be embedded in sensors as frontend processors for feature learning, encoding, and compression.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134183052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Integration of Si-CMOS and III-V materials through multi-wafer stacking 通过多晶圆堆叠集成Si-CMOS和III-V材料
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309243
K. Lee, Li Zhang, B. Wang, S. C. Goh, Shuyu Bao, Yue Wang, W. A. Sasangka, K. Lee, E. Fitzgerald, C. S. Tan
{"title":"Integration of Si-CMOS and III-V materials through multi-wafer stacking","authors":"K. Lee, Li Zhang, B. Wang, S. C. Goh, Shuyu Bao, Yue Wang, W. A. Sasangka, K. Lee, E. Fitzgerald, C. S. Tan","doi":"10.1109/S3S.2017.8309243","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309243","url":null,"abstract":"A method to integrate III-V compound semiconductors (e.g., GaN HEMT, InGaN LED, InGaAs HEMT or AlGaInP LED) and Si-CMOS on a common Si substrate is demonstrated. The Si-CMOS layer from SOI wafer is temporarily held on a Si handle wafer. Another III-V/Si substrate is then bonded to the Si-CMOS containing handle wafer. Finally, the handle wafer is released to realize the Si-CMOS on III-V/Si substrate. Additional III-V/Si substrates with different materials and structures can be integrated on the same piece of Si-CMOS+III-V/Si substrate by stacking another III-V/Si substrate before the handle wafer is removed. Through this method, integration of Si-CMOS with more than one type of III-V materials on a single Si platform can be realized (e.g., CMOS/InGaAs HEMT/GaN LED on a silicon substrate). Hence, a new generation of system with diversed functionalities, better energy efficiency, and smaller form factor can be achieved.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125214072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A wide range 60 GHz VCO using back-gate controlled varactor in 22 nm FDSOI technology 采用22nm FDSOI技术的后门控制变容器件实现宽范围60ghz压控振荡器
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309268
Chi Zhang, M. Otto
{"title":"A wide range 60 GHz VCO using back-gate controlled varactor in 22 nm FDSOI technology","authors":"Chi Zhang, M. Otto","doi":"10.1109/S3S.2017.8309268","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309268","url":null,"abstract":"This paper presents a 60 GHz, 34% tuning range mm-wave voltage-controlled oscillator (VCO). The VCO is fabricated in GLOBALFOUDRIES 22 nm FDSOI (22FDXTM) process. Switched capacitor based tuning array covers frequency range from 51 GHz to 72 GHz. A novel back-gate controlled varactor is used to achieve a low Kv of 680 MHz at 57 GHz carrier frequency. The power dissipation of VCO core is 7.5 mW from a 0.7 V supply when it operates at 60 GHz. The phase noise at 60 GHz carrier frequency is −84 dBc/Hz and −109 dBc/Hz, at 1MHz and 10MHz offset frequency, respectively.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133797787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 1,000x improvement in computer systems by bridging the processor-memory gap 通过弥合处理器和内存之间的差距，使计算机系统的性能提高了1000倍
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309202
Z. Or-Bach
{"title":"A 1,000x improvement in computer systems by bridging the processor-memory gap","authors":"Z. Or-Bach","doi":"10.1109/S3S.2017.8309202","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309202","url":null,"abstract":"For over 4 decades the gap between computer processing speed and memory access has grown at about 50% per year, to more than 1,000x today. This provides an excellent opportunity to enhance the single-core system performance. An innovative 3D integration technology combined with re-architecting the integrated memory device is proposed to bridge the gap and enable a 1,000 x improvement in computer systems. The proposed technology utilizes processes that are widely available and could be integrated in products within a very short time.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129486961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Advanced characterization technique for the extraction of intrinsic effective mobility in ultra-thin-body strained SOI MOSFETs 超薄体应变SOI mosfet本征有效迁移率提取的先进表征技术
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309238
Myungsoo Seo, H. Bae, C. Jeon, Byung-Hyun Lee, Yang‐Kyu Choi
{"title":"Advanced characterization technique for the extraction of intrinsic effective mobility in ultra-thin-body strained SOI MOSFETs","authors":"Myungsoo Seo, H. Bae, C. Jeon, Byung-Hyun Lee, Yang‐Kyu Choi","doi":"10.1109/S3S.2017.8309238","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309238","url":null,"abstract":"An accurate method of extracting intrinsic effective mobility is proposed which considers the parasitic component and floating-body effects. The technique was verified with fabricated ultra-thin body (UTB) strained silicon-on-insulator (sSOI) MOSFETs. The accurate mobility values extracted using the newly proposed technique, were then comparatively analyzed. This novel method corrects the underestimation of mobility produced by the parasitic component and the overestimated mobility resulting from the floating-body effects.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131736124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2.9nW ultra-low power ripple-voltage MPPT for autonomous miniature sensor nodes 用于自主微型传感器节点的2.9nW超低功耗纹波电压MPPT
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309251
Katrine Lundager, F. Moradi
{"title":"A 2.9nW ultra-low power ripple-voltage MPPT for autonomous miniature sensor nodes","authors":"Katrine Lundager, F. Moradi","doi":"10.1109/S3S.2017.8309251","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309251","url":null,"abstract":"A new technique based on a ripple-voltage MPPT in combination with a 2-phase charge pump structure for autonomous miniature sensor nodes is proposed. Compared to earlier techniques, the proposed technique reduces the power consumption of the MPPT by 92 % to 2.9 nW. Furthermore, a series-parallel charge pump in a 2-phase structure is proposed that achieves a high accuracy with low input and output ripple-voltage, allowing a smaller input buffer capacitance.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128820089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 11.5pW/bit 400mV 5T gain-cell eDRAM for ULP applications in 28nm FD-SOI 11.5pW/bit 400mV 5T增益单元eDRAM，用于28nm FD-SOI的ULP应用
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308757
R. Giterman, A. Teman, A. Fish
{"title":"A 11.5pW/bit 400mV 5T gain-cell eDRAM for ULP applications in 28nm FD-SOI","authors":"R. Giterman, A. Teman, A. Fish","doi":"10.1109/S3S.2017.8308757","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308757","url":null,"abstract":"The silicon area of ultra-low power (ULP) applications is often dominated by embedded memories, which are the main consumers of both the static and dynamic power in these applications [1]. Supply voltage scaling down to the sub-threshold region is widely used to significantly reduce both the static and dynamic power dissipation of ULP applications [2]. However, embedded memories, typically implemented with SRAM, have been the limiting factor for aggressive voltage scaling, since the conventional 6-transistor (6T) SRAM bitcell becomes unreliable at near-threshold operating voltages [3-6].","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121386919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Ultra-low-power dual-phase latch based digital accelerator for continuous monitoring of wheezing episodes 超低功耗双相锁存器为基础的连续监测喘息发作数字加速器
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308752
Patricia Gonzalez-Guerrero, M. Stan
{"title":"Ultra-low-power dual-phase latch based digital accelerator for continuous monitoring of wheezing episodes","authors":"Patricia Gonzalez-Guerrero, M. Stan","doi":"10.1109/S3S.2017.8308752","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308752","url":null,"abstract":"We designed an ultra-low-power accelerator for the calculation of the Short Time Fourier Transform (STFT) optimized for wheezing detection. The low power consumption of our accelerator relies on optimizations at different stages of the design process. Post-layout simulations show that at the minimum energy point our accelerator consumes 3.3 pJ/cycle at 0.5 V and 163 KHz. We compare the energy consumption of our implementation with its flip-flop version. Simulations show that we can save up to 50% in energy consumption for a latch based design vs. a flip-flop based design, making dual-phase latch based implementations excellent candidates for ultra-low-power devices.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122747799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信