面向低功耗应用的自级联编码SOI纳米线nmosfet模拟性能

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI:10.1109/S3S.2017.8309218

R. Assalti, M. de Souza, M. Cassé, S. Barraud, G. Reimbold, M. Vinet, O. Faynot

{"title":"面向低功耗应用的自级联编码SOI纳米线nmosfet模拟性能","authors":"R. Assalti, M. de Souza, M. Cassé, S. Barraud, G. Reimbold, M. Vinet, O. Faynot","doi":"10.1109/S3S.2017.8309218","DOIUrl":null,"url":null,"abstract":"This paper experimentally explores the analog performance of Self-Cascode structures composed by SOI Nanowire nMOSFETs operating near the subthreshold regime. The composite structure uses transistors with distinct channel widths, biased in several back-gate voltages, to promote different threshold voltages.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Analog performance of self-cascode SOI nanowires nMOSFETs aiming at low-power applications\",\"authors\":\"R. Assalti, M. de Souza, M. Cassé, S. Barraud, G. Reimbold, M. Vinet, O. Faynot\",\"doi\":\"10.1109/S3S.2017.8309218\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper experimentally explores the analog performance of Self-Cascode structures composed by SOI Nanowire nMOSFETs operating near the subthreshold regime. The composite structure uses transistors with distinct channel widths, biased in several back-gate voltages, to promote different threshold voltages.\",\"PeriodicalId\":333587,\"journal\":{\"name\":\"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/S3S.2017.8309218\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/S3S.2017.8309218","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文通过实验研究了由SOI纳米线nmosfet组成的自级联码结构在亚阈值附近的模拟性能。该复合结构采用具有不同通道宽度的晶体管，在多个后门电压中偏置，以促进不同的阈值电压。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Analog performance of self-cascode SOI nanowires nMOSFETs aiming at low-power applications

This paper experimentally explores the analog performance of Self-Cascode structures composed by SOI Nanowire nMOSFETs operating near the subthreshold regime. The composite structure uses transistors with distinct channel widths, biased in several back-gate voltages, to promote different threshold voltages.

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来源期刊

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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