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2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)最新文献

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Definite influence of substrate-contact condition on SOI substrate impedance parameters 衬底接触条件对SOI衬底阻抗参数的影响是明确的
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309261
Isao Yarita, Shingo Sato, Y. Omura
{"title":"Definite influence of substrate-contact condition on SOI substrate impedance parameters","authors":"Isao Yarita, Shingo Sato, Y. Omura","doi":"10.1109/S3S.2017.8309261","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309261","url":null,"abstract":"To better understand the pseudo-MOS structure, the influences of native oxide on the back surface of the SOI wafer and contact condition with the metal chuck on impedance are analyzed. When the initial resistance value of the back contact after HF treatment is low, the resistance slowly increases with time after HF treatment. This suggests that native oxide is hardly formed on the back surface when the SOI wafer is in good contact with the metal chuck.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122417232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Experimental analysis of differential pairs designed with line tunnel FET devices 用线隧道场效应晶体管设计差分对的实验分析
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308756
M. D. V. Martino, J. Martino, P. Agopian, R. Rooyackers, E. Simoen, N. Collaert, C. Claeys
{"title":"Experimental analysis of differential pairs designed with line tunnel FET devices","authors":"M. D. V. Martino, J. Martino, P. Agopian, R. Rooyackers, E. Simoen, N. Collaert, C. Claeys","doi":"10.1109/S3S.2017.8308756","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308756","url":null,"abstract":"The aim of this work is to study, for the first time, the behavior of differential pair circuits designed with Line TFETs and compare the suitability of this technology with alternatives such as FinFETs and Point TFETs. The first part highlights experimental characteristics of individual Line TFET transistors, which present similar transconductance and better output conductance when compared to FinFETs, while revealing better transconductance and worse output conductance in comparison to Point TFETs. Next, the experimental data for Line TFET differential pairs is presented for different bias conditions and dimensions. The last part compares the intrinsic voltage gain (Ad), the compliance voltage and susceptibility to channel length mismatch for the 3 technologies. It is explained that Line TFET presents the highest Ad, FinFETs provides a wider operation region and Point TFETs are the least susceptible to channel length variations.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116513486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Advanced FDSOI design: The U-channel device for 7nm node and beyond 先进的FDSOI设计:7nm及以上节点的u通道器件
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308747
R. Muralidhar, R. Dennard, T. Ando, I. Lauer, T. Hook
{"title":"Advanced FDSOI design: The U-channel device for 7nm node and beyond","authors":"R. Muralidhar, R. Dennard, T. Ando, I. Lauer, T. Hook","doi":"10.1109/S3S.2017.8308747","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308747","url":null,"abstract":"Planar ultra-thin body and box (UTBB1–3) fully depleted silicon on insulator (FDSOI) devices have many advantages for future low-cost energy-efficient applications. However, process steps for scaling to ultra-thin FDSOI devices can be difficult to control, and extrinsic resistance can hinder any performance improvement. In this paper, we present a novel planar U-channel UTBB FDSOI device that can alleviate these problems.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127796175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An ultra-low-power FPGA for IoT applications 用于物联网应用的超低功耗FPGA
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308753
He Qi, Oluseyi A. Ayorinde, B. Calhoun
{"title":"An ultra-low-power FPGA for IoT applications","authors":"He Qi, Oluseyi A. Ayorinde, B. Calhoun","doi":"10.1109/S3S.2017.8308753","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308753","url":null,"abstract":"The rapid development of the Internet-of-Things requires hardware that is both energy-efficient and flexible, and an ultra-low-power Field-Programmable-Gate-Array (FPGA) is a very promising solution. This paper presents a near/sub-threshold FPGA with low-swing global interconnect, folded switch box (SB), per-path voltage scaling, and power-gating. A fully programmable 512-look-up-table FPGA chip is fabricated in 130nm CMOS. When implementing a 4bit-adder, the measured energy of the proposed FPGA is 15% less than the normalized energy of the state-of-the-art. When implementing fifteen selected low-power applications, the estimated energy of the proposed FPGA is on average 75x lower than Microsemi IGLOO.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114566033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Enhanced design performance thanks to adaptative body biasing technique in FDSOI technolologies FDSOI技术中的自适应体偏置技术提高了设计性能
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308754
F. Arnaud, S. Clerc, S. Haendler, R. Bingert, P. Flatresse, V. Huard, T. Poiroux
{"title":"Enhanced design performance thanks to adaptative body biasing technique in FDSOI technolologies","authors":"F. Arnaud, S. Clerc, S. Haendler, R. Bingert, P. Flatresse, V. Huard, T. Poiroux","doi":"10.1109/S3S.2017.8308754","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308754","url":null,"abstract":"This paper presents a comprehensive analysis of Adaptive Body Bias (ABB) interests provided by Fully Depleted Silicon On Insulator (FDSOI) technology. At transistor level, we demonstrate a total process variability and temperature effect compensation thanks reverse and forward bias. Those benefits have been reached without degradation of devices reliability versus regular Adaptative Voltage Scaling solution (AVS). Leveraging this triple advantages (variability, temperature and ageing), digital design density is discussed showing significant reduction of W/L metric in case of ABB usage in CPU core. Forward Body Biasing (FBB) exhibited significant analog performance increasing (+100%) on key parameters such as gm and gd for both I/Os and core oxide devices. Finally, outstanding Vmin yield improvement thanks to ABB technique is demonstrated on commercial product in the automotive market.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123250641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Lateral spacers influence on the effective channel length of junctionless nanowire transistors 横向间隔对无结纳米线晶体管有效沟道长度的影响
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309260
R. Trevisoli, R. Doria, M. de Souza, M. Pavanello
{"title":"Lateral spacers influence on the effective channel length of junctionless nanowire transistors","authors":"R. Trevisoli, R. Doria, M. de Souza, M. Pavanello","doi":"10.1109/S3S.2017.8309260","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309260","url":null,"abstract":"This work presents a deep analysis on the effect of lateral spacers on the performance of the Junctionless Nanowire Transistors. An analytical model to account for the spacer influence on the device electrical behavior is proposed and validated through numerical simulation results.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124644332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Generalized cost model for 3D systems 三维系统的广义代价模型
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309222
D. Gitlin, M. Vinet, S. Chéramy, Hughes Metras, O. Faynot, T. Signamarcheix, J. Lequepeys
{"title":"Generalized cost model for 3D systems","authors":"D. Gitlin, M. Vinet, S. Chéramy, Hughes Metras, O. Faynot, T. Signamarcheix, J. Lequepeys","doi":"10.1109/S3S.2017.8309222","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309222","url":null,"abstract":"Electronic systems require the integration of tightly coupled components manufactured with very dissimilar manufacturing technologies. Meeting the system requirements of performance, cost and power is a challenging task and new integration methodologies play a key role. A generalized cost model for 3D systems is presented that is applicable to both sequential and parallel 3D system integration. It takes into account yield multiplication effects in the case of sequential integration, and also reflects the additive nature of the cost for parallel integration. Example applications of this model are provided, starting with single chips undergoing Moore's law transitions, chiplets on interposers, wafer-to-wafer hybrid bonded components as well as chip-on-wafer 3D technologies.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125247800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A novel photodetector based on the interface coupling effect in silicon-on-insulator MOSFETs 基于绝缘体上硅mosfet界面耦合效应的新型光电探测器
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309231
J. Deng, J. Shao, B. Lu, Y. Chen, A. Zaslavsky, S. Cristoloveanu, M. Bawedin, J. Wan
{"title":"A novel photodetector based on the interface coupling effect in silicon-on-insulator MOSFETs","authors":"J. Deng, J. Shao, B. Lu, Y. Chen, A. Zaslavsky, S. Cristoloveanu, M. Bawedin, J. Wan","doi":"10.1109/S3S.2017.8309231","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309231","url":null,"abstract":"We report a novel CMOS-compatible photodetector with record responsivity built on a silicon-on-insulator (SOI) substrate. The operating mechanism is based on in the interface coupling effect in the SOI MOSFET, as confirmed by both TCAD simulations and experimental measurements on a prototype device fabricated using a simplified process flow.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127795863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design optimization for NEM relays implemented in BEOL layers 在BEOL层中实现NEM继电器的设计优化
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309249
U. Sikder, T. Liu
{"title":"Design optimization for NEM relays implemented in BEOL layers","authors":"U. Sikder, T. Liu","doi":"10.1109/S3S.2017.8309249","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309249","url":null,"abstract":"This work discusses design considerations for a nano-electro-mechanical (NEM) relay implemented with a standard CMOS fabrication process utilizing the back-end-of-line (BEOL) metal layers. The quasi-static and dynamic performances of the relay are simulated using Coventor MEMS+. Various design trade-offs are discussed. A design optimization scheme for minimizing the energy-delay product is presented.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127939919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Power and performance comparision of body bias in 28HPC and back bias in 22FDX 28HPC的体偏和22FDX的背偏的功率和性能比较
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309225
K. Zhao, Jian Wang, Jianzhong Li, Bo Yang, Haihua Wang, Mingjie Shen, Fang Yu, Liewei Xu
{"title":"Power and performance comparision of body bias in 28HPC and back bias in 22FDX","authors":"K. Zhao, Jian Wang, Jianzhong Li, Bo Yang, Haihua Wang, Mingjie Shen, Fang Yu, Liewei Xu","doi":"10.1109/S3S.2017.8309225","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309225","url":null,"abstract":"In this paper, the body bias in 28nm Bulk and the back bias in 22nm FDSOI are analyzed and compared from two aspects: power consumption and circuit performance. Taking a 65-stage ring oscillator (RO) with 4-level frequency divider as an example, transistor lengths are all set to 30nm, post simulation results show that, for 22FDX RO, the operating frequency can adjust from 57.8MHz to 206MHz, with the operating current varies from 24uA to 91uA; while for 28HPC, the bulk RO can only modulate the operating frequency from 92.8MHz to 127MHz, with the operating current varies from 67.8uA to 129uA. Therefore, from both view of power and performance, the adjust ability of 22FDX circuits with back bias are much stronger than that of 28HPC circuits with body bias.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129116186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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