D. Gitlin, M. Vinet, S. Chéramy, Hughes Metras, O. Faynot, T. Signamarcheix, J. Lequepeys
{"title":"三维系统的广义代价模型","authors":"D. Gitlin, M. Vinet, S. Chéramy, Hughes Metras, O. Faynot, T. Signamarcheix, J. Lequepeys","doi":"10.1109/S3S.2017.8309222","DOIUrl":null,"url":null,"abstract":"Electronic systems require the integration of tightly coupled components manufactured with very dissimilar manufacturing technologies. Meeting the system requirements of performance, cost and power is a challenging task and new integration methodologies play a key role. A generalized cost model for 3D systems is presented that is applicable to both sequential and parallel 3D system integration. It takes into account yield multiplication effects in the case of sequential integration, and also reflects the additive nature of the cost for parallel integration. Example applications of this model are provided, starting with single chips undergoing Moore's law transitions, chiplets on interposers, wafer-to-wafer hybrid bonded components as well as chip-on-wafer 3D technologies.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Generalized cost model for 3D systems\",\"authors\":\"D. Gitlin, M. Vinet, S. Chéramy, Hughes Metras, O. Faynot, T. Signamarcheix, J. Lequepeys\",\"doi\":\"10.1109/S3S.2017.8309222\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Electronic systems require the integration of tightly coupled components manufactured with very dissimilar manufacturing technologies. Meeting the system requirements of performance, cost and power is a challenging task and new integration methodologies play a key role. A generalized cost model for 3D systems is presented that is applicable to both sequential and parallel 3D system integration. It takes into account yield multiplication effects in the case of sequential integration, and also reflects the additive nature of the cost for parallel integration. Example applications of this model are provided, starting with single chips undergoing Moore's law transitions, chiplets on interposers, wafer-to-wafer hybrid bonded components as well as chip-on-wafer 3D technologies.\",\"PeriodicalId\":333587,\"journal\":{\"name\":\"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/S3S.2017.8309222\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/S3S.2017.8309222","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Electronic systems require the integration of tightly coupled components manufactured with very dissimilar manufacturing technologies. Meeting the system requirements of performance, cost and power is a challenging task and new integration methodologies play a key role. A generalized cost model for 3D systems is presented that is applicable to both sequential and parallel 3D system integration. It takes into account yield multiplication effects in the case of sequential integration, and also reflects the additive nature of the cost for parallel integration. Example applications of this model are provided, starting with single chips undergoing Moore's law transitions, chiplets on interposers, wafer-to-wafer hybrid bonded components as well as chip-on-wafer 3D technologies.