衬底接触条件对SOI衬底阻抗参数的影响是明确的

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI:10.1109/S3S.2017.8309261

Isao Yarita, Shingo Sato, Y. Omura

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引用次数: 0

摘要

为了更好地理解伪mos结构，分析了SOI晶圆背面天然氧化物以及与金属卡盘接触条件对阻抗的影响。当HF处理后的后触点初始电阻值较低时，随着HF处理后时间的延长，电阻值缓慢增大。这表明，当SOI晶圆与金属卡盘良好接触时，在背面几乎不会形成天然氧化物。

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Definite influence of substrate-contact condition on SOI substrate impedance parameters

To better understand the pseudo-MOS structure, the influences of native oxide on the back surface of the SOI wafer and contact condition with the metal chuck on impedance are analyzed. When the initial resistance value of the back contact after HF treatment is low, the resistance slowly increases with time after HF treatment. This suggests that native oxide is hardly formed on the back surface when the SOI wafer is in good contact with the metal chuck.

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2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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