用线隧道场效应晶体管设计差分对的实验分析

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI:10.1109/S3S.2017.8308756

M. D. V. Martino, J. Martino, P. Agopian, R. Rooyackers, E. Simoen, N. Collaert, C. Claeys

{"title":"用线隧道场效应晶体管设计差分对的实验分析","authors":"M. D. V. Martino, J. Martino, P. Agopian, R. Rooyackers, E. Simoen, N. Collaert, C. Claeys","doi":"10.1109/S3S.2017.8308756","DOIUrl":null,"url":null,"abstract":"The aim of this work is to study, for the first time, the behavior of differential pair circuits designed with Line TFETs and compare the suitability of this technology with alternatives such as FinFETs and Point TFETs. The first part highlights experimental characteristics of individual Line TFET transistors, which present similar transconductance and better output conductance when compared to FinFETs, while revealing better transconductance and worse output conductance in comparison to Point TFETs. Next, the experimental data for Line TFET differential pairs is presented for different bias conditions and dimensions. The last part compares the intrinsic voltage gain (Ad), the compliance voltage and susceptibility to channel length mismatch for the 3 technologies. It is explained that Line TFET presents the highest Ad, FinFETs provides a wider operation region and Point TFETs are the least susceptible to channel length variations.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Experimental analysis of differential pairs designed with line tunnel FET devices\",\"authors\":\"M. D. V. Martino, J. Martino, P. Agopian, R. Rooyackers, E. Simoen, N. Collaert, C. Claeys\",\"doi\":\"10.1109/S3S.2017.8308756\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The aim of this work is to study, for the first time, the behavior of differential pair circuits designed with Line TFETs and compare the suitability of this technology with alternatives such as FinFETs and Point TFETs. The first part highlights experimental characteristics of individual Line TFET transistors, which present similar transconductance and better output conductance when compared to FinFETs, while revealing better transconductance and worse output conductance in comparison to Point TFETs. Next, the experimental data for Line TFET differential pairs is presented for different bias conditions and dimensions. The last part compares the intrinsic voltage gain (Ad), the compliance voltage and susceptibility to channel length mismatch for the 3 technologies. It is explained that Line TFET presents the highest Ad, FinFETs provides a wider operation region and Point TFETs are the least susceptible to channel length variations.\",\"PeriodicalId\":333587,\"journal\":{\"name\":\"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"volume\":\"140 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/S3S.2017.8308756\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/S3S.2017.8308756","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

这项工作的目的是首次研究用线tfet设计的差分对电路的行为，并将该技术与finfet和点tfet等替代技术的适用性进行比较。第一部分重点介绍了单个线型TFET晶体管的实验特性，与finfet相比，它们具有相似的跨导性和更好的输出电导，而与点型TFET相比，它们具有更好的跨导性和更差的输出电导。其次，给出了不同偏置条件和尺寸下的线型TFET差分对的实验数据。最后比较了三种技术的固有电压增益(Ad)、顺应电压和对通道长度不匹配的敏感性。它解释了线TFET表现出最高的Ad, finfet提供更宽的工作区域，而点TFET最不容易受到通道长度变化的影响。

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Experimental analysis of differential pairs designed with line tunnel FET devices

The aim of this work is to study, for the first time, the behavior of differential pair circuits designed with Line TFETs and compare the suitability of this technology with alternatives such as FinFETs and Point TFETs. The first part highlights experimental characteristics of individual Line TFET transistors, which present similar transconductance and better output conductance when compared to FinFETs, while revealing better transconductance and worse output conductance in comparison to Point TFETs. Next, the experimental data for Line TFET differential pairs is presented for different bias conditions and dimensions. The last part compares the intrinsic voltage gain (Ad), the compliance voltage and susceptibility to channel length mismatch for the 3 technologies. It is explained that Line TFET presents the highest Ad, FinFETs provides a wider operation region and Point TFETs are the least susceptible to channel length variations.

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来源期刊

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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