{"title":"Lateral spacers influence on the effective channel length of junctionless nanowire transistors","authors":"R. Trevisoli, R. Doria, M. de Souza, M. Pavanello","doi":"10.1109/S3S.2017.8309260","DOIUrl":null,"url":null,"abstract":"This work presents a deep analysis on the effect of lateral spacers on the performance of the Junctionless Nanowire Transistors. An analytical model to account for the spacer influence on the device electrical behavior is proposed and validated through numerical simulation results.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/S3S.2017.8309260","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This work presents a deep analysis on the effect of lateral spacers on the performance of the Junctionless Nanowire Transistors. An analytical model to account for the spacer influence on the device electrical behavior is proposed and validated through numerical simulation results.