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2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)最新文献

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Towards 500°C SPER activated devices for 3D sequential integration 面向500°C的SPER激活设备，用于3D顺序集成
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309220
J. Micout, B. Sklénard, P. Batude, R. Berthelon, Q. Rafhay, J. Lacord, B. Mathieu, L. Pasini, Z. Saghi, V. Delaye, L. Brunet, C. Fenouillet-Béranger, S. Joblot, F. Mazen, V. Mazzocchi, J. Colinge, G. Ghibaudo, M. Vinet
{"title":"Towards 500°C SPER activated devices for 3D sequential integration","authors":"J. Micout, B. Sklénard, P. Batude, R. Berthelon, Q. Rafhay, J. Lacord, B. Mathieu, L. Pasini, Z. Saghi, V. Delaye, L. Brunet, C. Fenouillet-Béranger, S. Joblot, F. Mazen, V. Mazzocchi, J. Colinge, G. Ghibaudo, M. Vinet","doi":"10.1109/S3S.2017.8309220","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309220","url":null,"abstract":"This work investigates the possibility to reduce the Solid Phase Epitaxy Regrowth (SPER) temperature for dopant activation needed in 3D sequential integration. The electrical results obtained on 28nm FDSOI devices show that 500°C SPER can yield similar performance to that of 600°C SPER and 1050°C spike anneal. This paper highlights the advantages of using a <100>-oriented channel and tilted implantation to successfully reduce the SPER thermal budget. It also confirms that the channel can be used as a seed for the recrystallization. The analysis takes into account the SPER rate dependence on temperature, crystalline orientation, dopant type and dopant concentration.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122152128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 0.148nJ/conversion 65nm SOTB temperature sensor LSI using thermistor-defined current source 采用热敏电阻定义电流源的0.148nJ/转换65nm SOTB温度传感器LSI
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309211
Shinya Nii, K. Ishibashi
{"title":"A 0.148nJ/conversion 65nm SOTB temperature sensor LSI using thermistor-defined current source","authors":"Shinya Nii, K. Ishibashi","doi":"10.1109/S3S.2017.8309211","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309211","url":null,"abstract":"This paper presents an ambient temperature sensor LSI utilizing a thermistor which defines the current of the CCO (current controlled oscillator) on 65nm SOTB process. The temperature sensor measures the ambient temperature with the power consumption of 531nW and 0.148nJ/conversion. This occupies an area of 5863μm<sup>2</sup>. The measurement temperature range was from −50 ° C to 50 ° C, and the resolution was 0.04 ° C.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128139216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ultra low energy cryptographic engine designs and SOTB chip fabrication services in Japan 日本超低能量密码引擎设计和SOTB芯片制造服务
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309223
M. Ikeda
{"title":"Ultra low energy cryptographic engine designs and SOTB chip fabrication services in Japan","authors":"M. Ikeda","doi":"10.1109/S3S.2017.8309223","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309223","url":null,"abstract":"This presentation covers chip fabrication services on SOI devices in Japanese universities, and demonstrate ultra-low energy cryptographic engine design as an example of SOI chip fabrication. VLSI Design and Education Center (VDEC) has established in 1996 as a inter-university facility at the University of Tokyo. VDEC provides chip fabrication services, major EDA tools, and seminars for chip designs to Japanese universities for academic purposes. Through the VDEC activities, we have provided several chip fabrication services on SOI, including 0.15um FDSOI, 0.6um SOI, 0.35um BiCMOS SOI, 28nm FDSOI, and 65nm FDSOI. As a design example of 65nm FDSOI, namely, SOTB, This presentation will describe ultra-low energy ECDSA design.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128956935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Gate controlled diode characteristics of super steep subthreshold slope PN-body tied SOI-FET for high efficiency RF energy harvesting 用于高效射频能量收集的超陡亚阈斜率pn体束缚soi场效应管的门控二极管特性
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309230
Shun Momose, J. Ida, Takayuki Mori, Takahiro Yoshida, Jumpei Iwata, Takashi Horii, Takahiro Furuta, K. Itoh, K. Ishibashi, Y. Arai
{"title":"Gate controlled diode characteristics of super steep subthreshold slope PN-body tied SOI-FET for high efficiency RF energy harvesting","authors":"Shun Momose, J. Ida, Takayuki Mori, Takahiro Yoshida, Jumpei Iwata, Takashi Horii, Takahiro Furuta, K. Itoh, K. Ishibashi, Y. Arai","doi":"10.1109/S3S.2017.8309230","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309230","url":null,"abstract":"Gate controlled diode (GCD) characteristics with our newly proposed super steep subthreshold slope (SS) “PN-Body Tied SOI-FET” was shown, for the first time, compared with the conventional diodes. It shows the super steep characteristics, the low leakage current and the sharp On-characteristics even on the ultralow voltage range of 50mV. The simple circuit simulations also indicated that the GCD with “PN-Body Tied SOI-FET” will achieve the high efficiency rectification on the ultralow input power of the RF energy harvesting. Additionally, the slight shift of the voltage of the zero current was confirmed as a specific characteristics on this GCD.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1641 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123371386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Projected performance of experimental InAs/GaAsSb/GaSb TFET as millimeter-wave detector 实验用InAs/GaAsSb/GaSb TFET作为毫米波探测器的预测性能
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309216
J. Zhang, C. Alessandri, P. Fay, A. Seabaugh, T. Ytterdal, E. Memišević, L. Wernersson
{"title":"Projected performance of experimental InAs/GaAsSb/GaSb TFET as millimeter-wave detector","authors":"J. Zhang, C. Alessandri, P. Fay, A. Seabaugh, T. Ytterdal, E. Memišević, L. Wernersson","doi":"10.1109/S3S.2017.8309216","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309216","url":null,"abstract":"Based on measurements of a vertical nanowire InAs/GaAsSb/GaSb tunneling field-effect transistor (TFET) that exhibited minimum subthreshold swing of 48 mV/dec and a record high I<inf>60</inf> of 0.31 μA/μm, a SPICE model has been generated to allow an experimentally-based prediction of the nanowire TFET technology. At 30 GHz the detector has been simulated to reveal a sensitivity of 4.8 kV/W biased near zero volts (V<inf>GS</inf> = −0.06 V, V<inf>DS</inf> = 0.1 V). A maximum sensitivity of over 4000 kV/W has been obtained under biased conditions. These results exceed prior measurements of an In<inf>0</inf>.<inf>53</inf>Ga<inf>0</inf>.<inf>47</inf>As/ GaAs<inf>0</inf>.<inf>5</inf>Sb<inf>0</inf>.<inf>5</inf> heterojunction TFET by over an order of magnitude.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128521935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimizing TSPC frequency dividers for always-on low-frequency applications in 28nm FDSOI CMOS 优化TSPC分频器，用于28nm FDSOI CMOS中始终在线的低频应用
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308751
Pengcheng Xu, C. Gimeno, D. Bol
{"title":"Optimizing TSPC frequency dividers for always-on low-frequency applications in 28nm FDSOI CMOS","authors":"Pengcheng Xu, C. Gimeno, D. Bol","doi":"10.1109/S3S.2017.8308751","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308751","url":null,"abstract":"True Single Phase Clocked (TSPC) flip-flops (FF) are widely used in high-frequency dividers for their higher operation speed and lower power compared to Master-Slaver FFs. In this paper, we study the optimization of TSPC frequency dividers for always-on low-frequency clock division in ultra-low-power (ULP) SoCs. We analyze the architecture, operation principle and data loss problem in TSPC-based frequency divider. An optimization strategy based on selective gate length upsize is proposed to minimize power consumption by balancing switching and leakage power consumption. A 10-stage frequency divider was designed in 28 nm FDSOI CMOS and integrated in a ULP SoC. Post-layout simulations with 32-MHz input frequency show a power consumption of 28.3 nW with 0.8-V supply voltage.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115283458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
First demonstration of symmetric lateral NPN transistors on SOI featuring epitaxially-grown emitter/collector regions 在SOI上首次展示了具有外延生长发射极/集电极区域的对称横向NPN晶体管
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309229
P. Hashemi, J. Yau, Kevin K. H. Chan, T. Ning, G. Shahidi
{"title":"First demonstration of symmetric lateral NPN transistors on SOI featuring epitaxially-grown emitter/collector regions","authors":"P. Hashemi, J. Yau, Kevin K. H. Chan, T. Ning, G. Shahidi","doi":"10.1109/S3S.2017.8309229","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309229","url":null,"abstract":"We report the first demonstration of symmetric lateral NPN transistors on SOI having epitaxially-grown emitter/collector (E/C). Employing a novel notch-assisted epitaxy scheme, using faceted Si epi as RIE mask to expose the vertical intrinsic-base epi-seeding surfaces, the epitaxial E/C are automatically connected to extension regions for metal contact and/or for electrical probing. Healthy device I-V characteristics were obtained with post-epi RTA. The results suggest a path forward for devices suitable for low-power THz electronics applications.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122156198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Investigation of short-channel effects in 2D negative-capacitance field-effect transistors 二维负电容场效应晶体管的短沟道效应研究
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 1900-01-01 DOI: 10.1109/S3S.2017.8308758
W. You, Chih-Peng Tsai, P. Su
{"title":"Investigation of short-channel effects in 2D negative-capacitance field-effect transistors","authors":"W. You, Chih-Peng Tsai, P. Su","doi":"10.1109/S3S.2017.8308758","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308758","url":null,"abstract":"In this work, the short-channel effects (SCEs) in negative-capacitance FETs with 2D-material channel (2D-NCFET) are systematically investigated through numerical simulation corroborated by a theoretical 2D-NCFET subthreshold model. Our study reveals that, due to the impact of drain coupling on the negative-capacitance effect, the 2D-NCFET exhibits distinct SCEs. Additionally, for a given equivalent oxide thickness (EOT), the dielectric constant of the high-K interlayer can significantly alter the subthreshold characteristics of the short-channel 2D-NCFETs.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128510970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
New method for observing self-heating effect using transistor efficiency signature 利用晶体管效率特征观测自热效应的新方法
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 1900-01-01 DOI: 10.1109/S3S.2017.8309259
C. A. Mori, P. Agopian, J. Martino
{"title":"New method for observing self-heating effect using transistor efficiency signature","authors":"C. A. Mori, P. Agopian, J. Martino","doi":"10.1109/S3S.2017.8309259","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309259","url":null,"abstract":"This paper reports a new method for observing the presence of self-heating effect through transistor efficiency (gm/ID) signature from DC measurements, for fast and accurate analysis. This new method is tested first through numerical simulations employing simple analytical models, and then applied experimentally. The transistor efficiencies of short and long channel pFinFETs were used for experimental observation of self-heating effects in this paper. It is possible to see if the self-heating is weak, moderate or strong through the signature format observed on gm/ID versus ID curve.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115259643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A subthreshold 30pJ/bit self-timed ring based true random number generator for internet of everything 一个基于亚阈值30pJ/bit自定时环的万物互联真随机数发生器
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 1900-01-01 DOI: 10.1109/s3s.2017.8308742
Mathieu Coustans, C. Terrier, T. Eberhardt, Stephanie Salgado, A. Cherkaoui, L. Fesquet
{"title":"A subthreshold 30pJ/bit self-timed ring based true random number generator for internet of everything","authors":"Mathieu Coustans, C. Terrier, T. Eberhardt, Stephanie Salgado, A. Cherkaoui, L. Fesquet","doi":"10.1109/s3s.2017.8308742","DOIUrl":"https://doi.org/10.1109/s3s.2017.8308742","url":null,"abstract":"This paper presents a true random number generator that exploits the subthreshold properties of jitter of events propagating in a self-timed ring and jitter of events propagating in an inverter based ring oscillator. Design was implemented in 180nm CMOS flash process. Devices provide high quality random bit sequences passing FIPS 140-2 and NIST SP 800-22 statistical tests which guaranty uniform distribution and unpredictability thanks to the physics based entropy source.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124963696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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