Ultra low energy cryptographic engine designs and SOTB chip fabrication services in Japan

This presentation covers chip fabrication services on SOI devices in Japanese universities, and demonstrate ultra-low energy cryptographic engine design as an example of SOI chip fabrication. VLSI Design and Education Center (VDEC) has established in 1996 as a inter-university facility at the University of Tokyo. VDEC provides chip fabrication services, major EDA tools, and seminars for chip designs to Japanese universities for academic purposes. Through the VDEC activities, we have provided several chip fabrication services on SOI, including 0.15um FDSOI, 0.6um SOI, 0.35um BiCMOS SOI, 28nm FDSOI, and 65nm FDSOI. As a design example of 65nm FDSOI, namely, SOTB, This presentation will describe ultra-low energy ECDSA design.