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2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)最新文献

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Gate-induced vs. implanted body doping impact on Z2-FET DC operation 栅极诱导与植入体掺杂对Z2-FET直流工作的影响
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308748
C. Navarro, F. Gámiz, N. Rodriguez, L. Donetti, C. Sampedro, Seong-Il Kim, Y. Kim, S. Cristoloveanu
{"title":"Gate-induced vs. implanted body doping impact on Z2-FET DC operation","authors":"C. Navarro, F. Gámiz, N. Rodriguez, L. Donetti, C. Sampedro, Seong-Il Kim, Y. Kim, S. Cristoloveanu","doi":"10.1109/S3S.2017.8308748","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308748","url":null,"abstract":"The impact of the gate-induced virtual and body implanted doping on the DC Z2-FET operation is analyzed under several gate-biasing scenarios. Results are compared with related architectures such as the Shockley and P-I-N diodes or the current-gate thyristor. Gate biasing turns out to be essential to observe the characteristic sharp switch of Z2-FET device.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115710882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
New steep-slope device of comprehensive properties enhancement with hybrid operation mechanism for ultra-low-power applications 新型综合性能增强的超低功耗混合操作机构陡坡装置
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308755
Ru Huang, Qianqian Huang, Yang Zhao, Cheng Chen, Rundong Jia, Chunlei Wu, Jiaxin Wang, Lingyi Guo, Yangyuan Wang
{"title":"New steep-slope device of comprehensive properties enhancement with hybrid operation mechanism for ultra-low-power applications","authors":"Ru Huang, Qianqian Huang, Yang Zhao, Cheng Chen, Rundong Jia, Chunlei Wu, Jiaxin Wang, Lingyi Guo, Yangyuan Wang","doi":"10.1109/S3S.2017.8308755","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308755","url":null,"abstract":"A kind of new steep-slope device with hybrid operation mechanism, which is multi-finger Schottky barrier TFET (MFSB-TFET), is presented for the comprehensive electric properties enhancement, by using the strong points but avoiding the critical issues of different mechanisms. The device can experimentally achieve higher on current from the dominant Schottky current, appreciably reduced off-leakage current from self-depletion effect, and steeper slope from dominant tunneling current with enhanced junction electric field. From circuit design perspective, the MFSB-TFET performance in terms of output behavior, capacitance, delay, gain, noise, variability and reliability are also experimentally benchmarked. The MFSB-TFET with comprehensively superior performance shows great potentials for ultra-low-power circuit applications.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116162201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Differential input output CMOS (DINO-CMOS) — High performance and energy efficient logic family 差分输入输出CMOS (DINO-CMOS) -高性能和节能的逻辑系列
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309253
M. Haber, I. Levi, Y. Yehoshua, A. Fish
{"title":"Differential input output CMOS (DINO-CMOS) — High performance and energy efficient logic family","authors":"M. Haber, I. Levi, Y. Yehoshua, A. Fish","doi":"10.1109/S3S.2017.8309253","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309253","url":null,"abstract":"Conventional static CMOS logic is the most popular circuit design style in today's digital designs. For many years CMOS logic gates have been preferred mainly for their rail-to-rail swings, strong on/off states, robust operation, large noise margins and low static power. However, one of the main drawbacks of CMOS gates is the need to implement complementary computation networks: the NMOS based pulldown network (PDN) and the pull-up (PUN) PMOS network. Both networks (depending on the logic function of gate) consist of a few stacked transistors. The number of stacked transistors increases with the increase of the Fan-In of the gate, which usually requires upsizing these transistors to improve performance and noise margins. This issue is even more crucial in gates such as NORs, where low mobility stacked PMOS transistors significantly limit the performance of the gate and require large transistors, thus increasing the intrinsic capacitance and power dissipation of the gate. An example of a conventional CMOS NOR3 gate is shown in Fig. 1(a).","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114194791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Self-heating assessment and cold current extraction in FDSOI MOSFETs FDSOI mosfet的自热评估与冷流提取
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309239
K. Triantopoulos, M. Cassé, L. Brunet, P. Batude, C. Fenouillet-Béranger, G. Reimbold, G. Ghibaudo
{"title":"Self-heating assessment and cold current extraction in FDSOI MOSFETs","authors":"K. Triantopoulos, M. Cassé, L. Brunet, P. Batude, C. Fenouillet-Béranger, G. Reimbold, G. Ghibaudo","doi":"10.1109/S3S.2017.8309239","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309239","url":null,"abstract":"We present an experimental study of thermal effects in thin film FDSOI MOSFETs, with a focus on the impact of self-heating effect (SHE) on drain current. We have performed thermal resistance extraction using the gate thermometry method, and calculated the resulting cold drain current (Id0), i.e. without SHE. We demonstrate that SHE is more pronounced in shorter and narrower devices without essential differences between nMOS and pMOS transistors. Our experiments show that although the temperature increases significantly in the channel due to SHE, its effect on the ION performances could be limited at operating voltage.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121246475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Balancing pull-in and adhesion stability margins in non-volatile NEM switches 平衡非易失性NEM开关的拉入和粘附稳定裕度
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309215
G. Usai, L. Hutin, U. Sikder, J. L. Muñoz-Gamarra, T. Ernst, T. K. Liu, M. Vinet
{"title":"Balancing pull-in and adhesion stability margins in non-volatile NEM switches","authors":"G. Usai, L. Hutin, U. Sikder, J. L. Muñoz-Gamarra, T. Ernst, T. K. Liu, M. Vinet","doi":"10.1109/S3S.2017.8309215","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309215","url":null,"abstract":"This work provides guidelines aiming at obtaining a functional, non-volatile and reprogrammable NEM relay design for ultra-low power hybrid NEMS/CMOS circuits addressing various non-volatile memory applications operating at a fixed supply voltage Vdd.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132106228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Secured Dual-Rail-Precharge Mux-based (DPMUX) symmetric-logic for low voltage applications 低压应用的安全双轨预充多路复用(DPMUX)对称逻辑
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309254
David Zooker Zabib, I. Levi, A. Fish, O. Keren
{"title":"Secured Dual-Rail-Precharge Mux-based (DPMUX) symmetric-logic for low voltage applications","authors":"David Zooker Zabib, I. Levi, A. Fish, O. Keren","doi":"10.1109/S3S.2017.8309254","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309254","url":null,"abstract":"Hardware implementations of cryptographic algorithms may leak information through numerous side channels, which can be used to reveal the secret cryptographic keys, and therefore compromise the security of the algorithm. Power Analysis Attacks (PAAs) [1] exploit the information leakage from the device's power consumption (typically measured on the supply and/or ground pins). Digital circuits consume dynamic switching energy when data propagate through the logic in each new calculation (e.g. new clock cycle). The average power dissipation of a design can be expressed by: Ptot(t) = α · (Pd(t) + Ppvt(t)) (1) where α is the activity factor (the probability that the gate will switch) and depends on the probability distribution of the inputs to the combinatorial logic. This induces a linear relationship between the power and the processed data [2]. Pd is the deterministic power dissipated by the switching of the gate, including any parasitic and intrinsic capacitances, and hence can be evaluated prior to manufacturing. Ppvt is the change in expected power consumption due to nondeterministic parameters such as process variations, mismatch, temperature, etc. In this manuscript, we describe the design of logic gates that induce data-independent (constant) α and Pd.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133466945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
SNM analytical approach to robust subthreshold SRAM operation based on the 55nm DDC technology 基于55nm DDC技术的稳健亚阈值SRAM运行SNM分析方法
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308741
N. Misawa, H. Kurata, Kazuyuki Kumeno, R. Nanjo, M. Kai, T. Ema, M. Solé
{"title":"SNM analytical approach to robust subthreshold SRAM operation based on the 55nm DDC technology","authors":"N. Misawa, H. Kurata, Kazuyuki Kumeno, R. Nanjo, M. Kai, T. Ema, M. Solé","doi":"10.1109/S3S.2017.8308741","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308741","url":null,"abstract":"Subthreshold operational characteristics of Ultra-Low Leakage (ULL) 6T-SRAM bit-cell and circuit based on the 55nm deeply depleted channel (DDC) technology was evaluated. The maximum operation frequency was 5 to 20 MHz (TT @RT) under 0 to 0.34V range of forward back bias (VBB) condition and leakage current in the retention mode reduced down to 285fA/cell by reverse VBB. It was confirmed that the ULL SRAM has sufficient static noise margin (SNM) to operate in the subthreshold region by optimizing NMOS and PMOS VBB separately.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134422336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An implementation of 2RW dual-port SRAM using 65 nm Silicon-on-Thin-Box (SOTB) for smart IoT 采用65纳米薄盒硅(SOTB)实现2RW双端口SRAM，用于智能物联网
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309224
Yoshiki Yamamoto, T. Hasegawa, M. Yabuuchi, K. Nii, Yohei Sawada, S. Tanaka, Y. Shinozaki, Kyoji Ito, H. Shinkawata, S. Kamohara
{"title":"An implementation of 2RW dual-port SRAM using 65 nm Silicon-on-Thin-Box (SOTB) for smart IoT","authors":"Yoshiki Yamamoto, T. Hasegawa, M. Yabuuchi, K. Nii, Yohei Sawada, S. Tanaka, Y. Shinozaki, Kyoji Ito, H. Shinkawata, S. Kamohara","doi":"10.1109/S3S.2017.8309224","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309224","url":null,"abstract":"An embedded 2-read/write (2RW) dual-port (DP) SRAM using 65-nm Silicon-on-Thin-Box (SOTB) is demonstrated. 25.85 nW/Mbit ultra-low standby power is observed by applying back-bias (BB) control in the sleep mode, reduced to 1/1000 compared to the normal standby mode. The measured read access time with forward BB is 1.64 ns at 1.0 V overdrive and 25°C, which is 2.75x faster than that of normal mode at 0.75 V with zero-BB, achieving over 380 MHz operation. Read/write disturbance issues in DP SRAM are evaluated by test chips, confirmed there are no issues.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134040268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Heterogeneous integration toward monolithic 3D chip 面向单片三维芯片的异构集成
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309242
Sanghyeon Kim, S. Kim, J. Shim, Dae-Myeong Geum, Gunwu Ju, Hansung Kim, Hee Jung Lim, Hyeongrak Lim, Jaehoon Han, Chang-Mo Kang, Dong Seon Lee, J. Song, W. Choi, Hyung-jun Kim
{"title":"Heterogeneous integration toward monolithic 3D chip","authors":"Sanghyeon Kim, S. Kim, J. Shim, Dae-Myeong Geum, Gunwu Ju, Hansung Kim, Hee Jung Lim, Hyeongrak Lim, Jaehoon Han, Chang-Mo Kang, Dong Seon Lee, J. Song, W. Choi, Hyung-jun Kim","doi":"10.1109/S3S.2017.8309242","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309242","url":null,"abstract":"Monolithic 3D (M3D) integration has attracted lots of attentions to continue equivalent scaling by vertically stacking transistors [1]. It allows the reduction of the interconnect delay, resulting in reduction of the power consumption of the chip, which is the attractive driving force for M3D integration. Moreover, with M3D, many other components such as digital, analog, MEMS, sensors, etc. can be heterogeneously integrated together in a single chip to provide enhanced functionality (Fig. 1). In this context, M3D concept can have additional benefit by integrating two or more different materials [2]. Heterogeneous integration of different materials combined with M3D is more powerful, because each processes with different materials don't have to share same process step and sequence, allowing us more flexible process design and it naturally has many benefits from their advantageous physical properties.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121256504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
STT-MRAM for embedded memory applications from eNVM to last level cache 用于从eNVM到最后一级缓存的嵌入式内存应用程序的STT-MRAM
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308734
L. Thomas, G. Jan, S. Le, S. Serrano-Guisan, Yuan-Jen Lee, Huanlong Liu, Jian Zhu, J. Iwata-Harms, R. Tong, Sahil J. Patel, V. Sundar, D. Shen, Yi Yang, R. He, J. Haq, Z. Teng, V. Lam, Paul Liu, Yu-Jen Wang, T. Zhong, P. Wang
{"title":"STT-MRAM for embedded memory applications from eNVM to last level cache","authors":"L. Thomas, G. Jan, S. Le, S. Serrano-Guisan, Yuan-Jen Lee, Huanlong Liu, Jian Zhu, J. Iwata-Harms, R. Tong, Sahil J. Patel, V. Sundar, D. Shen, Yi Yang, R. He, J. Haq, Z. Teng, V. Lam, Paul Liu, Yu-Jen Wang, T. Zhong, P. Wang","doi":"10.1109/S3S.2017.8308734","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308734","url":null,"abstract":"Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) is emerging as a leading candidate for a variety of embedded memory applications ranging from embedded NVM to working memory and last level cache. In this paper, we review recent breakthroughs that have brought perpendicular STT-MRAM to the cusp of mass production.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122780715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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