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Physical implementation of low power SoC chip based on SEC 28nm FDS 基于SEC 28nm FDS的低功耗SoC芯片的物理实现
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309210
Jiong Zhu, S. Jin, Jun Chen
{"title":"Physical implementation of low power SoC chip based on SEC 28nm FDS","authors":"Jiong Zhu, S. Jin, Jun Chen","doi":"10.1109/S3S.2017.8309210","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309210","url":null,"abstract":"Low Power technologies are increasingly important, driven by the mobile device, IoT market, and the energy-saving. FD-SOI technology becomes more popular after few products successfully introduced in this process. It shows more possible methods to reduce the chip power consumption. This paper presents physical design of a Low Power SoC chip. The FD-SOI benchmark experience and customized IP design experience help to reduce the implementation schedule. We have developed dedicated 28nm FD-SOI IPs: USB2.0, MIPI DPHY, Audio CODEC, and the Low-power Memory. The physical implementation of the chip has been completed within 2 months.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123674070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Experimental comparative analysis between junctionless and inversion mode nanowire transistors down to 10 nm-long channel lengths 沟道长度小于10纳米的无结和反转模式纳米线晶体管的实验比较分析
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308749
R. Doria, R. Trevisoli, M. de Souza, M. Pavanello, M. Vinet, M. Cassé, O. Faynot
{"title":"Experimental comparative analysis between junctionless and inversion mode nanowire transistors down to 10 nm-long channel lengths","authors":"R. Doria, R. Trevisoli, M. de Souza, M. Pavanello, M. Vinet, M. Cassé, O. Faynot","doi":"10.1109/S3S.2017.8308749","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308749","url":null,"abstract":"This paper aims at presenting, for the first time, an experimental comparative analysis between the main electrical parameters of Junctionless (JNT) and inversion mode nanowire (IM) transistors fabricated in SOI technology down to channel length of 10 nm. The analysis has shown that JNTs present larger immunity to SCEs with respect to IM nanowires of similar dimensions. However, JNTs have shown poorer Ion than IM devices, which could be compensated through the application of multifin JNTs, at cost of increasing area consumption.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121760858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
0.45v and 18pA/MHz MCU SOC with advanced Adaptive Dynamic Voltage Control (ADVC) 0.45v和18pA/MHz MCU SOC，先进的自适应动态电压控制(ADVC)
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308745
Uzi Zangi, Neil Feldman, J. Shor, A. Fish
{"title":"0.45v and 18pA/MHz MCU SOC with advanced Adaptive Dynamic Voltage Control (ADVC)","authors":"Uzi Zangi, Neil Feldman, J. Shor, A. Fish","doi":"10.1109/S3S.2017.8308745","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308745","url":null,"abstract":"An Ultra-low power MCU SOC is described with integrated DC to DC power management and Adaptive Dynamic Voltage Control (ADVC) mechanism. The SOC includes the complete Synopsys ARC EM5D core MCU, featuring a full set of DSP instructions and minimizing energy consumption at a wide range of frequencies: 312K-80MHz. On-die Silicon sensors are utilized to continuously change the operating voltage to optimize power/performance for a given frequency and environmental conditions and also to resolve yield and life time problems while operating at low voltages. The core operates between 0.45–1.1V volts with a direct battery connection for an input voltage of 1.0–3.8V. The peak energy efficiency is 18μA/MHz. A comparison to state-of-the-art commercial SOCs is presented, showing a 3–5x improved current/DMIPS (Dhrystone Million Instructions per sec) compared to the next best chip.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127209293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A SPDT RF switch small- and large-signal characteristics on TR-HR SOI substrates 在TR-HR SOI基板上的SPDT射频开关小信号和大信号特性
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308737
B. K. Esfeh, S. Makovejev, F. Allibert, J. Raskin
{"title":"A SPDT RF switch small- and large-signal characteristics on TR-HR SOI substrates","authors":"B. K. Esfeh, S. Makovejev, F. Allibert, J. Raskin","doi":"10.1109/S3S.2017.8308737","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308737","url":null,"abstract":"This paper evaluates the small- and large-signal characteristics of a single pole double thru (SPDT) RF antenna switch including its insertion loss, isolation and non-linear behavior. It is fabricated on two different types of high resistivity (HR) Silicon-on-Insulator (SOI) substrates: one standard (HR-SOI) and one trap-rich (RFeSI80). Using a special test structure, the contribution of substrate and active devices is separated for both in small- and large-signal. It is shown that by using trap-rich substrate technology, a reduction of more than 17 dB of 2nd harmonic is achieved compared with HR SOI substrate.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127507994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
14nm FinFET technology SRAM cell margin evaluation and analysis by local layout effect 14nm FinFET技术SRAM电池裕度评估及局部布局效应分析
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309248
S. Mun, D. Burnett, K. Lim, S. Parihar, Y. Shi, H. Lo, W. Hong, K. Lee, O. Hu, J. Versaggi, C. Jerome, J. G. Lee, S. Samavedam, D. K. Sohn
{"title":"14nm FinFET technology SRAM cell margin evaluation and analysis by local layout effect","authors":"S. Mun, D. Burnett, K. Lim, S. Parihar, Y. Shi, H. Lo, W. Hong, K. Lee, O. Hu, J. Versaggi, C. Jerome, J. G. Lee, S. Samavedam, D. K. Sohn","doi":"10.1109/S3S.2017.8309248","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309248","url":null,"abstract":"14nm node SRAM using FinFETs with advanced Replacement Metal Gate (RMG) module shows sensitive Access Distuib Margin (ADM) response to Local Layout Effect (LLE) as seen in planar CMOS technology using RMG [1]. Additionally, 14nm FinFET technology has more LLEs than ever due to the layout variety or tighter minimum design rule applied [2]. Fluorine with very high reaction energy diffuses from WL CONT to Pass Gate (PG) is found to lower PG Vtsat degrading ß-ratio and ADM. And, the STI stress from strap cell reduces the SRAM NFET Vtsat of the cell at the array edge degrading ADM. The natural variation of Gate-cut to PG degrades the Vth mismatch resulting in ADM degradation also. These three kinds of LLE and their impacts on ADM are discussed and analyzed in detail in this paper along with mechanisms that can cause the LLEs.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126657629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Is there a Zero Temperature bias point (ZTC) on Back Enhanced (BE) SOI MOSFET? 反向增强SOI MOSFET是否存在零温度偏置点(ZTC) ?
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309258
L. Yojo, R. Rangel, K. Sasaki, J. Martino
{"title":"Is there a Zero Temperature bias point (ZTC) on Back Enhanced (BE) SOI MOSFET?","authors":"L. Yojo, R. Rangel, K. Sasaki, J. Martino","doi":"10.1109/S3S.2017.8309258","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309258","url":null,"abstract":"This paper reports the temperature influence on the Back Enhanced (BE) SOI MOSFET fabricated with two different source/drain contact electrodes: Ohmic and Schottky. The BE SOI MOSFET (Patent BR 102015020974-6, 2015) is a kind of undoped junction-less SOI transistor, which works like an n-type or p-type MOS, depending on the back bias conditions. In spite of the Schottky contact at source/drain is mandatory in order to have both type of transistor working in a similar way, the use of Ohmic contact may present some specials advantages. The results showed the presence of a ZTC (Zero Temperature Coefficient) bias condition only in the device with Ohmic source/drain contact. It was observed that the Schottky contact resistance decreased when the temperature increases resulting in a higher current and consequently the absence of the ZTC. This effect is explained through experimental measurements and simulation.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115241643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Reliability analysis on low temperature gate stack process steps for 3D sequential integration 三维顺序集成低温栅堆工艺步骤可靠性分析
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309219
A. Tsiara, X. Garros, C-M. V. Lu, C. Fenouillet-Béranger, P. Batude, R. Gassilloud, F. Martin, O. Faynot, G. Ghibaudo, G. Reimbold
{"title":"Reliability analysis on low temperature gate stack process steps for 3D sequential integration","authors":"A. Tsiara, X. Garros, C-M. V. Lu, C. Fenouillet-Béranger, P. Batude, R. Gassilloud, F. Martin, O. Faynot, G. Ghibaudo, G. Reimbold","doi":"10.1109/S3S.2017.8309219","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309219","url":null,"abstract":"In this study we investigate the effect of some of the steps during a low temperature gate stack process flow, necessary for 3D sequential integration. These are: the nitridation of the high-k layer, the post nitridation annealing temperature and finally, the back end forming gas. Using Time Dependent Defect Spectroscopy, we could evaluate the impact of pre-existing traps on the quality of the gate stack (t0 reliability) which shows no major differences between the splits, since they all have a low temperature dopant activation process. However, by applying Negative Bias Temperature Instability measurements, we observe that with the split of N2/H2 nitridation, we have the best compromise of a small Equivalent Oxide Thickness and a low degradation. At the same time we see no difference at the stress impact between the two Post Nitridation Anneal temperatures. In that way we are able to move to lower temperatures. Finally, using the Deuterium as a back end forming gas we can have a set of guidelines, for some of the major process steps, to achieve high performance and low degradation, necessary for future scaling.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128628641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Z2-FET SPICE model: DC and memory operation Z2-FET SPICE型号:DC和内存操作
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309240
S. Martinie, J. Lacord, O. Rozeau, M. Parihar, K. Lee, M. Bawedin, S. Cristoloveanu, Y. Taur, J. Barbe
{"title":"Z2-FET SPICE model: DC and memory operation","authors":"S. Martinie, J. Lacord, O. Rozeau, M. Parihar, K. Lee, M. Bawedin, S. Cristoloveanu, Y. Taur, J. Barbe","doi":"10.1109/S3S.2017.8309240","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309240","url":null,"abstract":"Z2-FET is a promising candidate for 1T-DRAM application. We report a pragmatic SPICE compact model, including DC and memory operation description. It is aligned with our TCAD simulations. The proposed model is based on V-I threshold voltage approach and it includes memorization effect. This model is implemented using Verilog-A and allows to evaluate, through SPICE simulation, the figures of merits for DC, transient and memory operation.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117075830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Monolithic integration of multiple III-V semiconductors on Si 多个III-V半导体在Si上的单片集成
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309200
H. Schmid, B. Mayer, J. Gooth, S. Wirths, L. Czornomaz, H. Riel, S. Mauthe, C. Convertino, K. Moselund
{"title":"Monolithic integration of multiple III-V semiconductors on Si","authors":"H. Schmid, B. Mayer, J. Gooth, S. Wirths, L. Czornomaz, H. Riel, S. Mauthe, C. Convertino, K. Moselund","doi":"10.1109/S3S.2017.8309200","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309200","url":null,"abstract":"We review our work on the direct epitaxy of III-V compounds on Si using template-assisted selective epitaxy (TASE) and demonstrate its use for the integration of electronic and optical devices. The III-V material is grown within the confined space given by an oxide template structure and lead to a III-V on insulator structure which can be further processed into devices. Monolithic integration of a broad range of III-V compounds enabled the fabrication of III-V FETs, TFETs, ballistic devices as well as optically pumped microdisk lasers on Si.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131793537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Review of progress in understanding the electron transport properties of amorphous chalcogenide phase change semiconductors (Invited paper) 非晶硫系相变半导体的电子输运性质研究进展(特邀论文)
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308733
Jie Liu
{"title":"Review of progress in understanding the electron transport properties of amorphous chalcogenide phase change semiconductors (Invited paper)","authors":"Jie Liu","doi":"10.1109/S3S.2017.8308733","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308733","url":null,"abstract":"The amorphous chalcogenide phase change semiconductors exhibit a series of peculiar yet technologically important electron transport properties, which have attracted intensive research attention in recent years. Despite their promising application scenario, these electron transport properties' fundamental governing physics remains an unsolved scientific puzzle which is still under debate. This paper reviews these measured peculiar electron transport properties, their technological significance, and their existing theoretical explanations. The open questions are summarized, in order to invoke further research attention.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122968176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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