Z2-FET SPICE型号:DC和内存操作

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI:10.1109/S3S.2017.8309240

S. Martinie, J. Lacord, O. Rozeau, M. Parihar, K. Lee, M. Bawedin, S. Cristoloveanu, Y. Taur, J. Barbe

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引用次数: 3

摘要

Z2-FET是一种很有前途的1T-DRAM应用候选者。我们报告了一个实用的SPICE紧凑模型，包括DC和内存操作描述。它与我们的TCAD模拟是一致的。该模型基于V-I阈值电压法，并考虑了记忆效应。该模型是使用Verilog-A实现的，并允许通过SPICE仿真来评估直流、瞬态和内存操作的优点。

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Z2-FET SPICE model: DC and memory operation

Z2-FET is a promising candidate for 1T-DRAM application. We report a pragmatic SPICE compact model, including DC and memory operation description. It is aligned with our TCAD simulations. The proposed model is based on V-I threshold voltage approach and it includes memorization effect. This model is implemented using Verilog-A and allows to evaluate, through SPICE simulation, the figures of merits for DC, transient and memory operation.

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2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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