采用65纳米薄盒硅(SOTB)实现2RW双端口SRAM，用于智能物联网

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI:10.1109/S3S.2017.8309224

Yoshiki Yamamoto, T. Hasegawa, M. Yabuuchi, K. Nii, Yohei Sawada, S. Tanaka, Y. Shinozaki, Kyoji Ito, H. Shinkawata, S. Kamohara

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引用次数: 2

摘要

演示了一种采用65纳米薄盒硅(SOTB)的嵌入式2读/写(2RW)双端口(DP) SRAM。通过在睡眠模式下应用反向偏置(BB)控制，观察到25.85 nW/Mbit的超低待机功率，与正常待机模式相比降低到1/1000。在1.0 V超速和25°C下，具有正向BB的读访问时间为1.64 ns，比正常模式在0.75 V零BB下的读访问时间快2.75倍，实现超过380 MHz的工作。通过测试芯片对DP SRAM的读写干扰问题进行了评估，确认没有问题。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An implementation of 2RW dual-port SRAM using 65 nm Silicon-on-Thin-Box (SOTB) for smart IoT

An embedded 2-read/write (2RW) dual-port (DP) SRAM using 65-nm Silicon-on-Thin-Box (SOTB) is demonstrated. 25.85 nW/Mbit ultra-low standby power is observed by applying back-bias (BB) control in the sleep mode, reduced to 1/1000 compared to the normal standby mode. The measured read access time with forward BB is 1.64 ns at 1.0 V overdrive and 25°C, which is 2.75x faster than that of normal mode at 0.75 V with zero-BB, achieving over 380 MHz operation. Read/write disturbance issues in DP SRAM are evaluated by test chips, confirmed there are no issues.

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来源期刊

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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