基于55nm DDC技术的稳健亚阈值SRAM运行SNM分析方法

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI:10.1109/S3S.2017.8308741

N. Misawa, H. Kurata, Kazuyuki Kumeno, R. Nanjo, M. Kai, T. Ema, M. Solé

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引用次数: 0

摘要

研究了基于55nm深度耗尽通道(DDC)技术的超低漏(ULL) 6T-SRAM位单元和电路的亚阈值工作特性。在0 ~ 0.34V正反偏置(VBB)条件下，最大工作频率为5 ~ 20 MHz (TT @RT)，反向VBB使保持模式下的漏电流降至285fA/cell。通过对NMOS和PMOS VBB分别进行优化，证实了ULL SRAM具有足够的静态噪声裕度(SNM)，可以在阈下区域工作。

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SNM analytical approach to robust subthreshold SRAM operation based on the 55nm DDC technology

Subthreshold operational characteristics of Ultra-Low Leakage (ULL) 6T-SRAM bit-cell and circuit based on the 55nm deeply depleted channel (DDC) technology was evaluated. The maximum operation frequency was 5 to 20 MHz (TT @RT) under 0 to 0.34V range of forward back bias (VBB) condition and leakage current in the retention mode reduced down to 285fA/cell by reverse VBB. It was confirmed that the ULL SRAM has sufficient static noise margin (SNM) to operate in the subthreshold region by optimizing NMOS and PMOS VBB separately.

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来源期刊

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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