Machine intelligence through 3D waferscale integration

Abstract

Bringing computing systems to the stage of Machine Intelligence will require a massive scaling in processing, memory, and interconnectivity, and thus a major change in how electronic systems are designed. Long overlooked because of its unsuitability for the exacting demands of enterprise computing, 3D waferscale integration offers a promising scaling path, due in large part to the fault-tolerant nature of many cognitive algorithms. This work explores this scaling path in greater detail, invoking a simple model of brain connectivity to examine the potential for 3D waferscale integration to meet the demanding interconnectivity requirements of Machine Intelligence.