Vertically-composed fine-grained 3D CMOS

Abstract

Parallel and monolithic 3D integration directions realize 3D integrated circuits (ICs) by utilizing layer-by-layer implementations. In contrast, vertically composed 3D CMOS has eluded us likely due to the seemingly insurmountable CMOS circuit style connectivity requirement in 3D. In this paper, we describe Skybridge-3D-CMOS (S3DC), an IC fabric that shows for the first time a pathway to achieve fine-grained static CMOS circuit implementations leveraging the vertical direction. It employs a new fabric assembly scheme based on pre-doped vertical nanowire bundles and implements CMOS circuits in and across nanowires. It utilizes innovative connectivity features to realize CMOS connectivity in 3D. Evaluation results, for the implemented benchmarks, show 72%–77% reductions in power consumption, 13X-16X increases in density, and 2% loss to 9% benefit in best operating frequencies compared with the state-of-art transistor-level monolithic 3D technology.