R. Gomez, C. Dutto, V. Huard, S. Clerc, E. Bano, P. Flatresse
{"title":"Design methodology with body bias: From circuit to engineering","authors":"R. Gomez, C. Dutto, V. Huard, S. Clerc, E. Bano, P. Flatresse","doi":"10.1109/S3S.2017.8309212","DOIUrl":null,"url":null,"abstract":"In this paper, a built-in Body Bias design methodology is proposed and implemented in two different contexts: the automotive industry and the IoT paradigm. As opposed to the traditional design strategy, the proposed methodology incorporates Body Bias in all design stages, from synthesis to engineering. Measurements performed in a leakage-driven ADAS product and a dual core application processor in 28nm UTBB-FDSOI technology confirm the effectiveness of the proposed methodology, achieving a 30% reduction in static power, 25% in dynamic power, 15% yield recovery, and a 4X frequency and 2X leakage spread reduction.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/S3S.2017.8309212","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
In this paper, a built-in Body Bias design methodology is proposed and implemented in two different contexts: the automotive industry and the IoT paradigm. As opposed to the traditional design strategy, the proposed methodology incorporates Body Bias in all design stages, from synthesis to engineering. Measurements performed in a leakage-driven ADAS product and a dual core application processor in 28nm UTBB-FDSOI technology confirm the effectiveness of the proposed methodology, achieving a 30% reduction in static power, 25% in dynamic power, 15% yield recovery, and a 4X frequency and 2X leakage spread reduction.