Die-level processing for 3-D monolithic integration of piezoelectric MEMS on CMOS

SMRs and FBARs allow for a wide variety of applications such as IR and mass sensors, RF filters, and signal generators. By integrating devices directly on CMOS, bonding and attachment parasitics can be eliminated, permitting the optimization of the design for each application. Using full wafers in a research environment is not cost-effective and developing a die process that allows the use of MPWs is of great benefit for research environments. In this work, we demonstrate several of the techniques that allow for 3D integration using small dies, and show the value of these techniques for piezoelectric MEMS structures.