A partitioning-free methodology for optimized gate-level monolithic 3D designs

Abstract

This paper presents a partitioning-free algorithm that transforms a 2D design into a gate-level Monolithic 3D one, reducing design footprint by 50%, total wire length by 15% and net switching power by at least 30% around iso-performance (considered with a 5% margin) for all the benchmark blocks (openMSP, FFT, LDPC and 128-bits AES) in 28nm technology.