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2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)最新文献

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32Kb Innovative fuse (I-Fuse) array in 22nm FD-SOI with 0.9V/1.4mA program voltage/current and 0.744um2 cell 创新的保险丝(I-Fuse)阵列，采用22nm FD-SOI，程序电压/电流为0.9V/1.4mA，电池面积为0.444 um2
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308735
Shine C. Chung, Wen-Kuan Fang, Jay Lin, Wen-Hua Yu, J. Hsiao
{"title":"32Kb Innovative fuse (I-Fuse) array in 22nm FD-SOI with 0.9V/1.4mA program voltage/current and 0.744um2 cell","authors":"Shine C. Chung, Wen-Kuan Fang, Jay Lin, Wen-Hua Yu, J. Hsiao","doi":"10.1109/S3S.2017.8308735","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308735","url":null,"abstract":"I-fuse is a revolutionary OTP programmed below an on-set of thermal runaway and above electromigration (EM) threshold. On 22nm FD-SOI, the 1R1T I-fuse has a 0.744um2 cell and 0.0312mm2 32Kb array with program voltage ranging from 0.9 V to 1.4 V. The whole array does not require high voltage circuits or charge pumps. The cell current distributions for data 0 and 1 are very tight and have large separation in between that can be sensed easily. The first cut design has been qualified at 150oC for 1,000 hours with very small cell current variations.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125221112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel in-situ resistance measurement to extract IMC resistivity and kinetic parameter for CoSn 3D stacks 一种新的原位电阻测量方法，用于提取CoSn三维叠层的IMC电阻率和动力学参数
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309244
L. Hou, J. Derakhshandeh, J. de Coster, Teng Wang, V. Cherman, P. Bex, K. Rebibis, Geert Van De Plas, G. Beyer, E. Beyne, I. De Wolf
{"title":"A novel in-situ resistance measurement to extract IMC resistivity and kinetic parameter for CoSn 3D stacks","authors":"L. Hou, J. Derakhshandeh, J. de Coster, Teng Wang, V. Cherman, P. Bex, K. Rebibis, Geert Van De Plas, G. Beyer, E. Beyne, I. De Wolf","doi":"10.1109/S3S.2017.8309244","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309244","url":null,"abstract":"Cobalt based UBM (under bump metallization) has the advantages of less UBM consumption, single and ductile IMC (intermetallic compound)) and no Kirkendall voids formation which makes it interesting for 3D stacking specially in fine pitch microbumps. In this paper for first time the electrical properties of Co-Sn IMC and kinetics of IMC growth are investigated by in-situ resistance measurement. Extracted parameters are verified by conventional cross section SEM analysis. This technique has the advantages of being non-destructive, quick and accurate measurement for any UBM and solder materials for 3D applications.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122066780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Hump-effect impact on subthreshold VLSI circuit 峰效应对亚阈值VLSI电路的影响
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309252
Mathieu Coustans, Darryl Gauthey, Sergio Rota, A. Acovic, P. Habaš, René Meyer
{"title":"Hump-effect impact on subthreshold VLSI circuit","authors":"Mathieu Coustans, Darryl Gauthey, Sergio Rota, A. Acovic, P. Habaš, René Meyer","doi":"10.1109/S3S.2017.8309252","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309252","url":null,"abstract":"This paper presents a comparative study of VLSI circuits operated in subthreshold and the impact of matching and hump-effect in a mature 180nm process. Measurement at device level is first presented. Then two circuits have been used to compare such as current reference, and SRAM, ROM are ultimately limited by noise level and mismatch. In this work, CORNER DOPED devices have been fabricated, measured, and finally compared with standard CMOS technology of the same area and a particular emphasis on weak inversion region. The proposed device shows improved gate voltage mismatch in weak inversion with respect to standard CMOS.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114642676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
New thermal management approach for transistor-level 3-D integtration 晶体管级三维集成的新热管理方法
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309205
Md Arif Iqbal, Mostafizur Rahman
{"title":"New thermal management approach for transistor-level 3-D integtration","authors":"Md Arif Iqbal, Mostafizur Rahman","doi":"10.1109/S3S.2017.8309205","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309205","url":null,"abstract":"Among various 3-D integration approaches for beyond 2-D CMOS logic, transistor based 3-D integrations such as monolithic 3-D [1], Skybridge [2], vertical Si nanowire CMOS [3], and vertical FET based integrated circuit [4] holds most promise. However, such integration approaches face thermal management challenges, since stacked transistors are detached from the substrate (i.e., heat sink). Traditional system level approaches such as liquid cooling [5], heat spreader [6], etc. are inadequate for transistor level 3-D integration and have huge cost overhead [7]. In this paper, we propose generic physical level heat management features transistor level 3-D integration and show their application through detailed thermal modeling and simulations. These features include a thermal junction and heat conducting pillar. The heat junction is a specialized junction to extract heat from a selected region in 3-D; it allows heat conduction without interference with the electrical activities of the circuit. In conjunction with the junction, our proposed thermal pillars enable heat dissipation through the substrate; these pillars are analogous to TSVs/Vias, but carry only heat. These structures are generic and can be applied to any transistor level 3-D integration approaches. Extending our previous work on Skybridge [8], we perform 3-D finite element based analysis to capture both static and transient thermal behaviors of 3-D circuits, and show the effectiveness of heat management features. Our simulation results show that proposed heat extraction feature is very effective in heat management, reducing temperature from heated area by up to 53%.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125820600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 65-nm SOTB implementation of a physically unclonable function and its performance improvement by body bias control 一种物理不可克隆功能的65纳米SOTB实现及其通过体偏置控制的性能改进
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309209
Y. Hori, T. Katashita, Y. Ogasahara
{"title":"A 65-nm SOTB implementation of a physically unclonable function and its performance improvement by body bias control","authors":"Y. Hori, T. Katashita, Y. Ogasahara","doi":"10.1109/S3S.2017.8309209","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309209","url":null,"abstract":"This study explores the feasibility of using silicon-on-thin-buried oxide (SOTB) devices for physically unclonable functions (PUFs) and the effect of body biasing of the SOTB on the performance of a PUF. The low variability of the SOTB is desirable for ultra-low-power operation of the circuit, whereas it can cause performance decrease in a PUF, because a PUF generates a unique chip ID by exploiting the device variability. This paper reports the feasibility of using a reduced-variability SOTB for a PUF for the first time. We fabricated arbiter PUFs in the 65-nm SOTB process and measured the PUF responses for core voltages in the range of 0.4–0.8 V and body bias in the range of −0.5–0.5 V. We demonstrated that the SOTB can be used to implement a PUF successfully, and its performance can be improved by adjusting the body bias of the SOTB.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123935262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
PVT compensation in Mie Fujitsu 55 nm DDC: A standard-cell library based comparison Mie Fujitsu 55nm DDC的PVT补偿:基于标准细胞库的比较
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309246
T. C. Müller, Jean-Luc Nagel, M. Pons, D. Séverac, Katsuhiro Hashiba, Shinichi Sawada, Katsuji Miyatake, S. Emery, A. Burg
{"title":"PVT compensation in Mie Fujitsu 55 nm DDC: A standard-cell library based comparison","authors":"T. C. Müller, Jean-Luc Nagel, M. Pons, D. Séverac, Katsuhiro Hashiba, Shinichi Sawada, Katsuji Miyatake, S. Emery, A. Burg","doi":"10.1109/S3S.2017.8309246","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309246","url":null,"abstract":"In this paper we characterize the cross corner and cell to cell variation of a custom standard cell library (SCL) in Mie Fujitsu 55nm Deeply Depleted Channel (DDC) technology. Precharacterized Liberty library files are used as a dataset for comparing both the unbiased library against a characterization using adaptive body biasing (ABB) to compensate for process voltage and temperature (PVT) variation. Results show a reduction of the cross corner median delay variation from 2154% down to 18% with the application of ABB.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127280704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Improving solder wetting of micro bumps on metal pads using metallic or organic pad coatings 使用金属或有机焊盘涂层改善金属焊盘上微凸起的焊料润湿性
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309263
I. de Preter, L. Hou, J. Derakhshandeh, P. Bex, F. Fodor, V. Cherman, K. Rebibis, Andy Miller
{"title":"Improving solder wetting of micro bumps on metal pads using metallic or organic pad coatings","authors":"I. de Preter, L. Hou, J. Derakhshandeh, P. Bex, F. Fodor, V. Cherman, K. Rebibis, Andy Miller","doi":"10.1109/S3S.2017.8309263","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309263","url":null,"abstract":"In this paper the passivation effect of thin electroless metallic layers such as Au, NiB or Immersion Sn or thin organic layers such as Self Assembled Monolayer (SAM) on Cu, Co and Ni UBM microbumps is studied during Thermo-Compression-Bonding (TCB) and after anneal with conditions that were identified to be equal to 10 years working device at 80°C on an electrical test vehicle. Characterization with X-section SEM is done to look at the wettability and joint formation and electrical resistance measurement are performed to determine the yield.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131048350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Blackghost 1.0 test chip: On the road towards commercializing ultra-low-Vdd SoC for Internet-of-Things Blackghost 1.0测试芯片:迈向物联网超低vdd SoC商用之路
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308750
Y. Pu, K. Easton, Chunlei Shi, R. Beraha, Adam Newham, Rashid Attar, Yang Du
{"title":"Blackghost 1.0 test chip: On the road towards commercializing ultra-low-Vdd SoC for Internet-of-Things","authors":"Y. Pu, K. Easton, Chunlei Shi, R. Beraha, Adam Newham, Rashid Attar, Yang Du","doi":"10.1109/S3S.2017.8308750","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308750","url":null,"abstract":"We introduce the Blackghost 1.0 SoC developed in Qualcomm Research, which is our first test chip that paved the road towards the commercialization of the ultra-low-Vdd Blackghost product family. Through seamless integration of many low-power innovations from software, hardware, architecture and circuit, Blackghost delivers unmatched power efficiency for battery-powered Internet-of-Things. It integrates a low footprint sensor/control processor based on ARM Cortex M0, an on-die power management unit with direct battery attach capability, a computer vision classifier processor, a programmable DSP hardware accelerator and an ultra-low-power analog front end on a 3×3 mm2 die in TSMC 28LP CMOS process technology. The computation can operate at near-threshold voltages (<0.6V) at frequencies up to 50 MHz and draws only <9 μA/MHz from the directly attached battery.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124932605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Theoretical investigation of backgate-biasing effects on ultrathin-body GeSn based tunneling FET 超薄体GeSn隧道场效应晶体管后门偏置效应的理论研究
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309214
Hongjuan Wang, G. Han, Yan Liu, Jincheng Zhang, Y. Hao, Xiangwei Jiang
{"title":"Theoretical investigation of backgate-biasing effects on ultrathin-body GeSn based tunneling FET","authors":"Hongjuan Wang, G. Han, Yan Liu, Jincheng Zhang, Y. Hao, Xiangwei Jiang","doi":"10.1109/S3S.2017.8309214","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309214","url":null,"abstract":"The impacts of backgate-biasing (K<inf>BS</inf>) on the performance of ultrathin-body (UTB) GeSn homo- and GeSn/SiGeSn type-II hetero-TFET are investigated via numerical simulation. A negative shift of onset voltage (K<inf>ONSET</inf>) is observed in both devices with K<inf>BS</inf> varying from −1 V to 1 V. Negative K<inf>BS</inf> provides higher on-state current (/<inf>ON</inf>) and steeper subthreshold swing (SS), as compared with the devices under K<inf>bs</inf> ≥ 0 V. This is due to the higher carrier generation rate and shorter tunneling path induced by negative K<inf>BS</inf>. Under the same backgate-bias condition, improved I<inf>ON</inf>, SS, and ambipolar characteristics are demonstrated in the hetero-TFETs over the homo devices.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129770796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design margin elimination through robust timing error detection at ultra-low voltage 设计余量消除通过鲁棒定时误差检测在超低电压
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308743
Hans Reyserhove, W. Dehaene
{"title":"Design margin elimination through robust timing error detection at ultra-low voltage","authors":"Hans Reyserhove, W. Dehaene","doi":"10.1109/S3S.2017.8308743","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308743","url":null,"abstract":"This paper discusses a timing error masking-aware ARM Cortex M0 microcontroller system. Through in-path timing error detection, operation at the point-of-first-failure is possible without corrupting the pipeline state, effectively eliminating traditional timing margins. Error events are flagged and gathered to allow dynamic voltage scaling. The error-aware microcontroller was implemented in a 40nm CMOS process and realizes ultra-low voltage operation down to 0.29V at 5MHz consuming 12.90pJ/cycle, or a MEP of 11.11pJ/cycle at 7.5MHz. Measurements show the in situ approach is ideal to overcome traditional SS corner design margins (75% energy reduction). Additionally it overcomes the limitations introduced by replica path based techniques typically plagued by intradie variations (8% reduction).","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129104865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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