{"title":"A 65-nm SOTB implementation of a physically unclonable function and its performance improvement by body bias control","authors":"Y. Hori, T. Katashita, Y. Ogasahara","doi":"10.1109/S3S.2017.8309209","DOIUrl":null,"url":null,"abstract":"This study explores the feasibility of using silicon-on-thin-buried oxide (SOTB) devices for physically unclonable functions (PUFs) and the effect of body biasing of the SOTB on the performance of a PUF. The low variability of the SOTB is desirable for ultra-low-power operation of the circuit, whereas it can cause performance decrease in a PUF, because a PUF generates a unique chip ID by exploiting the device variability. This paper reports the feasibility of using a reduced-variability SOTB for a PUF for the first time. We fabricated arbiter PUFs in the 65-nm SOTB process and measured the PUF responses for core voltages in the range of 0.4–0.8 V and body bias in the range of −0.5–0.5 V. We demonstrated that the SOTB can be used to implement a PUF successfully, and its performance can be improved by adjusting the body bias of the SOTB.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/S3S.2017.8309209","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This study explores the feasibility of using silicon-on-thin-buried oxide (SOTB) devices for physically unclonable functions (PUFs) and the effect of body biasing of the SOTB on the performance of a PUF. The low variability of the SOTB is desirable for ultra-low-power operation of the circuit, whereas it can cause performance decrease in a PUF, because a PUF generates a unique chip ID by exploiting the device variability. This paper reports the feasibility of using a reduced-variability SOTB for a PUF for the first time. We fabricated arbiter PUFs in the 65-nm SOTB process and measured the PUF responses for core voltages in the range of 0.4–0.8 V and body bias in the range of −0.5–0.5 V. We demonstrated that the SOTB can be used to implement a PUF successfully, and its performance can be improved by adjusting the body bias of the SOTB.