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2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)最新文献

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GOI fabrication for monolithic 3D integration 用于单片式三维集成的 GOI 制造
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309201
A. Abedin, L. Zurauskaite, A. Asadollahi, K. Garidis, G. Jayakumar, B. Malm, P. Hellström, M. Östling
{"title":"GOI fabrication for monolithic 3D integration","authors":"A. Abedin, L. Zurauskaite, A. Asadollahi, K. Garidis, G. Jayakumar, B. Malm, P. Hellström, M. Östling","doi":"10.1109/S3S.2017.8309201","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309201","url":null,"abstract":"A low temperature (T<inf>max</inf>=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si<inf>0</inf>.<inf>5</inf>Ge<inf>0</inf>.<inf>5</inf> as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 10<sup>16</sup> cm<sup>−3</sup> are achieved. Ge pFETs are fabricated (T<inf>max</inf>=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of −0.18 V and 60% higher mobility than the SOI pFET reference devices.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129133848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
System-level benchmark of synaptic device characteristics for neuro-inspired computing 神经启发计算的突触装置特性的系统级基准
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309197
Pai-Yu Chen, Xiaochen Peng, Shimeng Yu
{"title":"System-level benchmark of synaptic device characteristics for neuro-inspired computing","authors":"Pai-Yu Chen, Xiaochen Peng, Shimeng Yu","doi":"10.1109/S3S.2017.8309197","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309197","url":null,"abstract":"Synaptic devices based on emerging non-volatile memory devices have been proposed to emulate analog synapses for neuro-inspired computing. However, the non-ideal device characteristics such as nonlinear and asymmetric weight increase/decrease, and finite on/off ratio, may adversely affect the learning accuracy at the system-level. In this paper, we present a device-circuit-algorithm co-simulation framework, i.e. NeuroSim, to systematically the metrics such as accuracy, area, latency and energy for online learning with synaptic devices. We surveyed a few representative synaptic devices in literature, and concluded that today's realistic devices are difficult to achieve accurate and fast learning. Finally, the targeted and ideal specifications for synaptic device engineering are proposed.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126418344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Investigations on contact punch-through in 28 nm FDSOI through virtual fabrication 基于虚拟制造的28纳米FDSOI接触穿孔研究
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309236
B. Vianne, P. Morin, C. Beylier, J. Giraudin, S. Desmoulins, R. Gonella, A. Juncker, D. Fried
{"title":"Investigations on contact punch-through in 28 nm FDSOI through virtual fabrication","authors":"B. Vianne, P. Morin, C. Beylier, J. Giraudin, S. Desmoulins, R. Gonella, A. Juncker, D. Fried","doi":"10.1109/S3S.2017.8309236","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309236","url":null,"abstract":"The ultra-thin body-bias (UTBB) and fully- depleted silicon on insulator (FDSOI) 28nm technology offers the capability of extreme low power performance, in part because of the use of ultra-thin buried oxide. This unique capability could be jeopardized by the probability of over etching the buried oxide layer during the formation of contacts, with potential generation of electrical short with the substrate. We used SEMulator3D virtual fabrication platform from Coventor to model the contact punch-through mechanism. We then run a design of experiment with the model to quantify the sensitivity of each process variable. Finally we used the virtual fabrication methodology to improve the robustness of the process.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126193317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Opportunity of CMOS FD-SOI for RF power amplifier CMOS FD-SOI用于射频功率放大器的机会
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309264
B. Martineau, E. Mercier, P. Vincent
{"title":"Opportunity of CMOS FD-SOI for RF power amplifier","authors":"B. Martineau, E. Mercier, P. Vincent","doi":"10.1109/S3S.2017.8309264","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309264","url":null,"abstract":"This paper reports the design of a 5GHz WiFi power amplifier (PA) taking advantage of the FD-SOI technology. Fabricated in a 28nm UTBB FD-SOI process with 1.8-V thick oxide devices, the PA output exhibits 23dBm Psat, 18dBm under low distortion with a 3.7V power supply. The core occupies less than 1mm2 while integrating transformer and baluns.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126556107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A high-efficiency single-stage power amplifier for WLAN 802.11ac in 22nm FDSOI 用于WLAN 802.11ac的高效率单级功率放大器，采用22nm FDSOI
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309265
S. T. Lee, A. Bellaouar, S. Embabi
{"title":"A high-efficiency single-stage power amplifier for WLAN 802.11ac in 22nm FDSOI","authors":"S. T. Lee, A. Bellaouar, S. Embabi","doi":"10.1109/S3S.2017.8309265","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309265","url":null,"abstract":"A high efficient and high gain single-stage power amplifier for WLAN 802.11ac is presented. The design uses a pseudo-differential common source amplifier with high gm/I core devices and with two cascode stages before connecting to an on-chip transformer which performs impedance transformation and also converts the differential signal into single-ended before driving the 50Q load. The gate of the last cascode device is biased by the output signal feedback through an RC filter. The design has been fabricated using 22nm FDSOI process and operates from a power supply of 2.7V. It achieves PAE of 31% and a maximum gain of 22dB. The 1dB output compression point is 25dBm and gain variation is less than 1.4dB over the frequency range of 5170–5835MHz.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130660157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Study of Process Transconductance for Understanding Gate Capacitance of FDSOI NCFET 了解FDSOI nfet栅极电容的过程跨导研究
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309262
S. Qureshi, S. Mehrotra
{"title":"Study of Process Transconductance for Understanding Gate Capacitance of FDSOI NCFET","authors":"S. Qureshi, S. Mehrotra","doi":"10.1109/S3S.2017.8309262","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309262","url":null,"abstract":"We present simulation study of process transconductance parameter of FDSOI n-NCFET and FDSOI p-NCFET extracted from drain current vs drain-to-source voltage plots of respective devices in the linear region for different ferro-electric (PZT) thicknesses using FDSOI n-MOSFET and p-MOSFET as baseline devices which are identical with respective NCFET except the gate stack. The baseline device being in strong inversion, the carrier mobility is deduced from device process transconductance and used to determine the effective gate capacitance of NCFET for different PZT thicknesses.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"59 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133713202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
STI techniques for isolation of RF-SOI devices RF-SOI器件隔离的STI技术
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309255
Siva P Adusumilli, S. Shank, J. Ellis-Monaghan, Chu-hsiang Teng, M. D. Levy, A. Stamper
{"title":"STI techniques for isolation of RF-SOI devices","authors":"Siva P Adusumilli, S. Shank, J. Ellis-Monaghan, Chu-hsiang Teng, M. D. Levy, A. Stamper","doi":"10.1109/S3S.2017.8309255","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309255","url":null,"abstract":"Shallow trench isolation (STI) plays an important role in preventing current leakage between active semiconductor regions and enables the industry to scale device density. STI is created early during the device fabrication process, before transistors are formed. There are mainly two ways to create the isolation: through oxide growth between active shapes (referred to as LOCOS), and by etching the trenches, filling with dielectric and removing the excessive dielectric using chemical-mechanical planarization, which is a CMP based STI technique. CMP STI can be done in 3 ways namely direct, mask aligned (Process A) and self-aligned (Process B).","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131272130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel CV/GV technique for top and bottom BOX interfaces traps density extraction on FDSOI wafers FDSOI晶圆上、下BOX界面的CV/GV捕获技术
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8308736
W. Vandendaele, C. Malaquin, A. Ghorbel, M. Cassé, F. Allibert, G. Reimbold
{"title":"Novel CV/GV technique for top and bottom BOX interfaces traps density extraction on FDSOI wafers","authors":"W. Vandendaele, C. Malaquin, A. Ghorbel, M. Cassé, F. Allibert, G. Reimbold","doi":"10.1109/S3S.2017.8308736","DOIUrl":"https://doi.org/10.1109/S3S.2017.8308736","url":null,"abstract":"A novel capacitive structure embedding the FDSOI film serves as a test platform to extract Dit at top (film/BOX) and bottom (BOX/substrate) interfaces by a single CV/GV measurement. Fully depleted SOI (FDSOI) bare wafers interfaces quality is evaluated for the first time through CV/GVmeasurement and modeling and G/ω peaks fitting. The influence of FDSOI film thickness is evaluated on the specific G/ω peak amplitude related to top interface Dit.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133219492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Level-shifter free approach for multi-Vdd SOTB employing adaptive Vt modulation for pMOSFET 采用pMOSFET自适应Vt调制的多vdd SOTB免移电平方法
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309226
K. Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, H. Amano
{"title":"Level-shifter free approach for multi-Vdd SOTB employing adaptive Vt modulation for pMOSFET","authors":"K. Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, H. Amano","doi":"10.1109/S3S.2017.8309226","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309226","url":null,"abstract":"This paper proposes a level-shifter free (LSF) approach for multi-VDD design to employ a combination of body bias control and a superior threshold-voltage (Vt) modulation capability of SOTB (Silicon on Thin BOX) devices. We applied this approach to a microprocessor test chip with low-voltage (VDDL) and high-voltage (VDDH) domains, and fabricated it in a 65nm SOTB technology. Measurement results demonstrated that the chip correctly operates at VDDL=0.6V and VDDH=1.2V under the reverse-body-bias (RBB) of 2V for pMOS transistors in the VDDH domain while suppressing the static dc current.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130958582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Theoretical models for low-frequency noise behaviors of buried-channel MOSFETs 埋沟道mosfet低频噪声特性的理论模型
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI: 10.1109/S3S.2017.8309247
Y. Omura, Shingo Sato
{"title":"Theoretical models for low-frequency noise behaviors of buried-channel MOSFETs","authors":"Y. Omura, Shingo Sato","doi":"10.1109/S3S.2017.8309247","DOIUrl":"https://doi.org/10.1109/S3S.2017.8309247","url":null,"abstract":"This paper proposes theoretical models for the low-frequency noise behaviors of buried-channel SOI MOSFETs in the subthreshold bias range. The model suggests that the interface traps near the top surface of the SOI layer strongly modulate the current fluctuation of the buried channel.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123855637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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