{"title":"埋沟道mosfet低频噪声特性的理论模型","authors":"Y. Omura, Shingo Sato","doi":"10.1109/S3S.2017.8309247","DOIUrl":null,"url":null,"abstract":"This paper proposes theoretical models for the low-frequency noise behaviors of buried-channel SOI MOSFETs in the subthreshold bias range. The model suggests that the interface traps near the top surface of the SOI layer strongly modulate the current fluctuation of the buried channel.","PeriodicalId":333587,"journal":{"name":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Theoretical models for low-frequency noise behaviors of buried-channel MOSFETs\",\"authors\":\"Y. Omura, Shingo Sato\",\"doi\":\"10.1109/S3S.2017.8309247\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes theoretical models for the low-frequency noise behaviors of buried-channel SOI MOSFETs in the subthreshold bias range. The model suggests that the interface traps near the top surface of the SOI layer strongly modulate the current fluctuation of the buried channel.\",\"PeriodicalId\":333587,\"journal\":{\"name\":\"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/S3S.2017.8309247\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/S3S.2017.8309247","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Theoretical models for low-frequency noise behaviors of buried-channel MOSFETs
This paper proposes theoretical models for the low-frequency noise behaviors of buried-channel SOI MOSFETs in the subthreshold bias range. The model suggests that the interface traps near the top surface of the SOI layer strongly modulate the current fluctuation of the buried channel.