STI techniques for isolation of RF-SOI devices

Abstract

Shallow trench isolation (STI) plays an important role in preventing current leakage between active semiconductor regions and enables the industry to scale device density. STI is created early during the device fabrication process, before transistors are formed. There are mainly two ways to create the isolation: through oxide growth between active shapes (referred to as LOCOS), and by etching the trenches, filling with dielectric and removing the excessive dielectric using chemical-mechanical planarization, which is a CMP based STI technique. CMP STI can be done in 3 ways namely direct, mask aligned (Process A) and self-aligned (Process B).