一种优化栅极级单片三维设计的无分割方法

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI:10.1109/S3S.2017.8309221

O. Billoint, M. Brocard, S. Thuries, G. Berhault, H. Sarhan

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引用次数: 2

摘要

本文提出了一种无分区算法，可将2D设计转换为门级单片3D设计，在28nm技术中将所有基准块(openMSP, FFT, LDPC和128位AES)的同等性能(考虑5%的边际)下，将设计占地面积减少50%，总线长减少15%，净开关功率减少至少30%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A partitioning-free methodology for optimized gate-level monolithic 3D designs

This paper presents a partitioning-free algorithm that transforms a 2D design into a gate-level Monolithic 3D one, reducing design footprint by 50%, total wire length by 15% and net switching power by at least 30% around iso-performance (considered with a 5% margin) for all the benchmark blocks (openMSP, FFT, LDPC and 128-bits AES) in 28nm technology.

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来源期刊

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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