A study of interferences inside an RF switch array in 45nm SOI CMOS

Abstract

This paper presents a study of interferences inside an RF switch array, aiming to understand the design influences on interference characteristics. The 2×2 single-pole double/triple-throw (SP2T/SP3T) Tx/Rx band switch array, featuring a series-shunt topology with gate resistance and feed-forward capacitance (FFC) and covering low (699–894MHz) and high (1710–2155MHz) bands, was designed and fabricated in a 45nm SOI CMOS. The inter-band and inner-band interferences were characterized, which reveals that existing noise isolation techniques, e.g., substrate isolation and layout floor planning, are insufficient for interference reduction. It therefore calls for novel in-die interference elimination techniques.