3D technologies for analog/RF applications

A. Vandooren, B. Parvais, L. Witters, A. Walke, A. Vais, C. Merckling, D. Lin, N. Waldron, P. Wambacq, D. Mocuta, N. Collaert
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引用次数: 6

Abstract

In this work, we will review possible technology options for next generation wireless communication. Next to the introduction of specific device architectures and materials, dissimilar from standard Si CMOS, the challenge will lie in the co-integration of these non-Si technologies with CMOS to enable power efficient systems with high performance, in this case high speed and output power, and reduced form factor. Next to monolithic integration, sequential 3D, currently been investigated for LOGIC density scaling, can be one of the enablers, allowing to combine technologies with very different needs at a finer grain and thus higher density than traditional 3D-SOC and 3D-IC technologies.
用于模拟/射频应用的3D技术
在这项工作中,我们将审查下一代无线通信的可能技术选择。与标准的Si CMOS不同,除了引入特定的器件架构和材料之外,挑战在于将这些非Si技术与CMOS协同集成,以实现具有高性能的节能系统,在这种情况下,可以实现高速度和输出功率,并减小外形尺寸。继单片集成之后,目前正在研究的逻辑密度缩放的顺序3D可以成为推动者之一,允许在更细的颗粒上结合不同需求的技术,从而比传统的3D- soc和3D- ic技术具有更高的密度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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