45nm SOI CMOS射频开关阵列内部干扰研究

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2017-10-01 DOI:10.1109/S3S.2017.8309266

Chenkun Wang, Fei Lu, Qi Chen, Feilong Zhang, Cheng Li, Dawn Wang, Albert Z. H. Wang

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引用次数: 2

摘要

本文对射频开关阵列内部的干扰进行了研究，旨在了解设计对干扰特性的影响。采用45nm SOI CMOS设计并制作了2×2单极双/三投(SP2T/SP3T) Tx/Rx波段开关阵列，该开关阵列具有串联并联拓扑，具有栅极电阻和前馈电容(FFC)，覆盖低(699-894MHz)和高(1710-2155MHz)频段。对带间和带内干扰进行了表征，揭示了现有的噪声隔离技术，如衬底隔离和布局地板规划，不足以减少干扰。因此，需要新的模内干扰消除技术。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A study of interferences inside an RF switch array in 45nm SOI CMOS

This paper presents a study of interferences inside an RF switch array, aiming to understand the design influences on interference characteristics. The 2×2 single-pole double/triple-throw (SP2T/SP3T) Tx/Rx band switch array, featuring a series-shunt topology with gate resistance and feed-forward capacitance (FFC) and covering low (699–894MHz) and high (1710–2155MHz) bands, was designed and fabricated in a 45nm SOI CMOS. The inter-band and inner-band interferences were characterized, which reveals that existing noise isolation techniques, e.g., substrate isolation and layout floor planning, are insufficient for interference reduction. It therefore calls for novel in-die interference elimination techniques.

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来源期刊

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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