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Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.最新文献

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All lead free IGBT module with excellent reliability 全无铅IGBT模块，可靠性卓越
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487955
Y. Nishimura, K. Oonishi, A. Morozumi, E. Mochizuki, Y. Takahashi
{"title":"All lead free IGBT module with excellent reliability","authors":"Y. Nishimura, K. Oonishi, A. Morozumi, E. Mochizuki, Y. Takahashi","doi":"10.1109/ISPSD.2005.1487955","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487955","url":null,"abstract":"The subject of lead free solder application of IGBT module is reliability of solder under the insulated substrate in temperature cycling test. This paper presents all lead free IGBT modules with excellent reliability. This was achieved by optimizing of the thermal expansion coefficient of insulated substrate and using Sn-Ag-In solder.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122431464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Trench IGBT behaviour near to latch-up conditions 接近闭锁条件的沟槽IGBT行为
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487999
A. Muller, F. Pfirsch, D. Silber
{"title":"Trench IGBT behaviour near to latch-up conditions","authors":"A. Muller, F. Pfirsch, D. Silber","doi":"10.1109/ISPSD.2005.1487999","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487999","url":null,"abstract":"Trench IGBTs show very high stability against latching with appropriate layout of the p-body/trench distance. This is in accordance with the simulation results. Simulation of parallel devices resulted in unexpected alternating high current states indicating the possibility of moving filaments as has been reported from dynamic avalanche investigations","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122707305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
10kV Trench Gate IGBTs on 4H-SiC 4H-SiC上10kV沟槽栅igbt
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488011
Q. Zhang, H. Chang, M. Gomez, C. Bui, E. Hanna, J. Higgins, T. Isaacs-smith, J. Williams
{"title":"10kV Trench Gate IGBTs on 4H-SiC","authors":"Q. Zhang, H. Chang, M. Gomez, C. Bui, E. Hanna, J. Higgins, T. Isaacs-smith, J. Williams","doi":"10.1109/ISPSD.2005.1488011","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488011","url":null,"abstract":"For the first time, 10kV trench IGBTs on 4H-SiC have been demonstrated. The devices exhibit an absolute resistance (V/J) of 290 m:o cm 2 ; specific resistance, (GV/GJ) of 175 m:o cm 2 and a –7.5V turn-on voltage at 25qC; a 13m:o cm 2 of specific resistance and a –4V of turn-on voltage at 150qC. A uniquely deep trench structure is incorporated to improve the device forward characteristics by a carrier injection enhancement (IE) effect.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122831095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
1600V 4H-SiC UMOSFETs with dual buffer layers 具有双缓冲层的1600V 4H-SiC umosfet
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487988
Q. Zhang, M. Gomez, C. Bui, E. Hanna
{"title":"1600V 4H-SiC UMOSFETs with dual buffer layers","authors":"Q. Zhang, M. Gomez, C. Bui, E. Hanna","doi":"10.1109/ISPSD.2005.1487988","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487988","url":null,"abstract":"This paper presents the design and fabrication of 1600V 4H-SiC UMOSFETs with a novel dual buffer layer structure, which shortens the trench etching time by 2/spl times/ and achieves a high channel periphery density of 3330cm/cm/sup 2/ for low specific on-resistance. The device exhibits 50m/spl Omega/-cm/sup 2/ of specific on-resistance with /spl sim/1/spl mu/m of channel length, and could be further reduced with <1/spl mu/m channel length and optimal fabrication process.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130953251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Analysis and modeling of DMOS FBSOA limited by n-p-n leakage diffusion current 受n-p-n泄漏扩散电流限制的DMOS FBSOA分析与建模
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488018
M. Denison, M. Pfost, M. Stecher, D. Silber
{"title":"Analysis and modeling of DMOS FBSOA limited by n-p-n leakage diffusion current","authors":"M. Denison, M. Pfost, M. Stecher, D. Silber","doi":"10.1109/ISPSD.2005.1488018","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488018","url":null,"abstract":"Failure of DMOS self-heated in saturation below the avalanche threshold is usually related to an activation of the parasitic n-p-n transistor. In this work we show that the exponential increase of the leakage diffusion current of the n-p-n is sufficient to cause thermal runaway, even for a slightly reverse body-source bias caused by the internal ballasting source resistance. Adding this current contribution to a basic DMOS compact model allows simulating the thermal limit of large DMOS transistors considered as distributed electrothermal networks. To our knowledge it is the first report of a quantitative DMOS FBSOA model accounting for the instabilities driven by the temperature dependences of both MOS and n-p-n components","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"6 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127645071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Realization of robust 600V high side gate drive IC with a new isolated self-shielding structure 采用新型隔离自屏蔽结构实现稳健的600V高边极驱动集成电路
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487971
S.L. Kim, C. Jeon, M. Kim, J.J. Kim
{"title":"Realization of robust 600V high side gate drive IC with a new isolated self-shielding structure","authors":"S.L. Kim, C. Jeon, M. Kim, J.J. Kim","doi":"10.1109/ISPSD.2005.1487971","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487971","url":null,"abstract":"A robust high side gate driver IC adapting new self-shielding concept with perfect isolation structure is experimentally realized. The fully depleted p-isolation region with low doping impurity gets rid of the crosstalk problem caused by leakage currents, which is essential problem of 600V, rated HVIC using self-shielding structure, between two LDMOS used as level shifters. In addition, highly doped n+ buried layer in the high side island region of proposed structure has led good dV/dt immunity. An HVIC adapting proposed structure has shown 65 kV/us of dV/dt characteristics and good characteristics for high side IGBT driving.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"4568 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126572605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Novel low capacitance VDMOS device for switching and RF power amplification 用于开关和射频功率放大的新型低电容VDMOS器件
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487982
S. Sapp, P. Thorup, A. Challa
{"title":"Novel low capacitance VDMOS device for switching and RF power amplification","authors":"S. Sapp, P. Thorup, A. Challa","doi":"10.1109/ISPSD.2005.1487982","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487982","url":null,"abstract":"In this paper the development of a novel low voltage PLANAR gate VDMOS device and process is presented. The device architecture was developed to reduce output capacitance while maintaining low on-state resistance for use in power switching applications and RF power amplification. The 80V device employs charge-balance techniques to minimize on-resistance and also considers how to reduce output capacitance to reduce switching loss.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114145995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Zero Voltage Switching of a 1200V PT Clustered Insulated Gate Bipolar Transistor 1200V PT簇绝缘栅双极晶体管的零电压开关
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488001
M. Sweet, J. Nicholls, K. Vershinin, O. Spulber, L. Ngwendson, E. M. Sankara Narayanan
{"title":"Zero Voltage Switching of a 1200V PT Clustered Insulated Gate Bipolar Transistor","authors":"M. Sweet, J. Nicholls, K. Vershinin, O. Spulber, L. Ngwendson, E. M. Sankara Narayanan","doi":"10.1109/ISPSD.2005.1488001","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488001","url":null,"abstract":"For the first time the zero voltage switching performance of a 1.2kV punch through clustered insulated gate bipolar transistor is reported. Experimental analysis under a zero voltage switching operating condition shows a reduction in `on' energy losses of 20% for all temperatures considered, even though significant transient over-voltages occur. This effect is not seen in the static IV characteristics and is shown to be as a result of a short p well-to-p well spacing","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114865988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High breakdown voltage GaN Schottky barrier diode employing floating metal rings on AlGaN/GaN hetero-junction 在AlGaN/GaN异质结上采用浮动金属环的高击穿电压GaN肖特基势垒二极管
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487997
Seung-Chul Lee, M. Ha, J. Her, Soo-Seong Kim, Jiyong Lim, K. Seo, M. Han
{"title":"High breakdown voltage GaN Schottky barrier diode employing floating metal rings on AlGaN/GaN hetero-junction","authors":"Seung-Chul Lee, M. Ha, J. Her, Soo-Seong Kim, Jiyong Lim, K. Seo, M. Han","doi":"10.1109/ISPSD.2005.1487997","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487997","url":null,"abstract":"We have reported a lateral GaN SBDs on AlGaN/GaN hetero-junction employing floating metal rings (FMRs) which exhibit a very high breakdown voltage, a low leakage current and a low on-state voltage. We have obtained a very high breakdown voltage of 930V without any additional process step. We have also optimized design parameters of FMR, such as the space between main junction and FMR and the number of rings. Our experimental results show that FMR which is rather simple may be suitable for lateral GaN SBD.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124840680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A Rugged LDMOS for LBC5 Technology 基于LBC5技术的坚固型LDMOS
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488017
P. Hower, J. Lin, S. Pendharkar, B. Hu, J. Arch, J. Smith, T. Efland
{"title":"A Rugged LDMOS for LBC5 Technology","authors":"P. Hower, J. Lin, S. Pendharkar, B. Hu, J. Arch, J. Smith, T. Efland","doi":"10.1109/ISPSD.2005.1488017","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488017","url":null,"abstract":"This paper presents a new method of enhancing the SOA of n-channel Ldmos transistors. Attention is focused on those applications where “Electrical SOA” is important and where the power pulse time is typically a few µs or less. Typical applications include gate drives, H-bridge commutation, and self-protection against ESD pulses.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129750618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 74
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