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Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.最新文献

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Ultra-fast LIGBTs and superjunction devices in membrane technology 膜技术中的超快光与超结器件
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488002
F. Udrea, T. Trajkovic, C. Lee, D. Garner, X. Yuan, J. Joyce, N. Udugampola, G. Bonnet, D. Coulson, R. Jacques, M. Izmajlowicz, N. van der Duijn Schouten, Z. Ansari, P. Moyse, G. Amaratunga
{"title":"Ultra-fast LIGBTs and superjunction devices in membrane technology","authors":"F. Udrea, T. Trajkovic, C. Lee, D. Garner, X. Yuan, J. Joyce, N. Udugampola, G. Bonnet, D. Coulson, R. Jacques, M. Izmajlowicz, N. van der Duijn Schouten, Z. Ansari, P. Moyse, G. Amaratunga","doi":"10.1109/ISPSD.2005.1488002","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488002","url":null,"abstract":"Back-side etching of the entire silicon substrate under part of the drift region of a SOI power device was first proposed by Udrea and Amararunga (2004) and experimentally reported by Udrea et al. (2005). This technology concept enables high voltage devices to be embedded in a thin silicon/oxide membrane resulting in very significant improvements in breakdown ability and switching speed. This paper presents new results from advanced membrane high power devices and fully functional power ICs. Furthermore, record switching speeds for the LIGBT are reported. The feasibility of realising superjunction structures (3D Resurf) with breakdown capability in excess of 700V using this technology are also demonstrated","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133852985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
On the safe operating area of power Schottky diodes in avalanche conditions 雪崩条件下功率肖特基二极管安全工作区域的研究
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487991
A. Irace, G. Breglio, P. Spirito, A. Bricconi, D. Raffo, L. Merlin
{"title":"On the safe operating area of power Schottky diodes in avalanche conditions","authors":"A. Irace, G. Breglio, P. Spirito, A. Bricconi, D. Raffo, L. Merlin","doi":"10.1109/ISPSD.2005.1487991","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487991","url":null,"abstract":"The aim of this paper is to give an insight and a possible explanation of the limitations in the reverse bias safe operating area of power Schottky diodes. A consistent set of experimental data together with theoretical analysis and ATLAS simulations are presented to explain possible reasons of device failures.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133499253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High-Voltage Diamond Vertical Schottky rectifiers 高压菱形垂直肖特基整流器
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488015
W. Huang, T. Chow, J. Yang, J. Butler
{"title":"High-Voltage Diamond Vertical Schottky rectifiers","authors":"W. Huang, T. Chow, J. Yang, J. Butler","doi":"10.1109/ISPSD.2005.1488015","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488015","url":null,"abstract":"We have designed, simulated and experimentally demonstrated high-voltage vertical diamond Schottky rectifiers. The rectifiers were fabricated on free-standing homo-epi films with remarkably low p-type doping using a lift-off process. Theoretical calculations have been performed to determine the thickness and doping concentration of the drift region. Devices with 20mum epi layer have been shown to block 3.7kV and conduct 0.6 A/cm2 at 20V forward drop at 290degC. A very low hole mobility or doping concentration and a Schottky barrier height of 0.26eV have been estimated","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115457326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A New 80V 32x32ch Low Loss Multiplexer LSI for a 3D Ultrasound Imaging System 用于3D超声成像系统的新型80V 32x32ch低损耗多路复用LSI
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488025
K. Hara, J. Sakano, M. Mori, S. Tamano, R. Sinomura, K. Yamazaki
{"title":"A New 80V 32x32ch Low Loss Multiplexer LSI for a 3D Ultrasound Imaging System","authors":"K. Hara, J. Sakano, M. Mori, S. Tamano, R. Sinomura, K. Yamazaki","doi":"10.1109/ISPSD.2005.1488025","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488025","url":null,"abstract":"This paper presents a new concept for an 80V multiplexer LSI with the world's largest 32 times 32ch cross-point switches for a real-time 3D ultrasound imaging system. This system requires hundreds of thousands of high voltage electrical switches. We propose a new gate floating type analog switch circuit with thin gate oxide power MOSFETs and a low-loss gate driving method for this LSI. The developed LSI can handle plusmn40V at 15 MHz ultrasound signal with reasonably low power dissipation (10mW/LSI) and can operate at a 33 MHz clock frequency for the first scanning operation. The developed LSIs are assembled in a hand probe and show a fine 3D volume image","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132155523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
A scalable trench etch based process for high voltage vertical RESURF MOSFETs 一种基于可扩展沟槽蚀刻的高压垂直复用mosfet工艺
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487944
C. Rochefort, R. Dalen
{"title":"A scalable trench etch based process for high voltage vertical RESURF MOSFETs","authors":"C. Rochefort, R. Dalen","doi":"10.1109/ISPSD.2005.1487944","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487944","url":null,"abstract":"In this work, for the first time, vertical RESURF MOSFETs manufactured using a trench etch and vapor phase doping process depict a breakdown voltage above 300V. We prove that this concept is scalable to a much higher breakdown voltage range. The device features a record low specific resistance of 0.98/spl Omega/mm/sup 2/ with a breakdown voltage of 473V. This best result to-date for any superjunction technology proves to be a good alternative to the multi-epitaxy technique commercially in use.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127262854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
ESD Scalability of LDMOS Devices for Self-Protected Output Drivers 用于自保护输出驱动器的LDMOS器件的ESD可扩展性
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488023
Young S. Chung, Hongzhong Xu, R. Ida, W. Min, B. Baird
{"title":"ESD Scalability of LDMOS Devices for Self-Protected Output Drivers","authors":"Young S. Chung, Hongzhong Xu, R. Ida, W. Min, B. Baird","doi":"10.1109/ISPSD.2005.1488023","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488023","url":null,"abstract":"Lateral DMOS (LDMOS) power transistors of SMART technologies are widely used as output drivers in multiple applications. However, LDMOS devices are generally not robust under ESD due to deep snapback causing localized current crowding and leading to inhomogeneous triggering of the parasitic bipolar, ESD ruggedness of LDMOS power devices has been a significant subject in smart power IC technology. Lack of understanding in geometry scalability of the LDMOS devices often thwarts a proper implementation of self-protected structures. Therefore, it is necessary to understand the ESD scalability and failure mechanism of the power output devices to meet various levels of design requirement and optimize ESD protection solution. LDMOS devices ESD capability has been understood from snapback breakdown of the parasitic bipolar components. They usually show different behavior under ESD stress conditions, compared to the normal MOS transistors. The triggering mechanism of the snapback breakdown has been major subjects in terms of device structures and designs. In this paper, we report an ESD capability and scalability of the LDMOS devices from the geometry and operational aspects, employing both experimental and simulation data. Difference of transient electrical behaviors and failure mechanisms of DMOS with different geometries under ESD stress conditions is also addressed","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128605575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Investigations on the ruggedness limit of 6.5 kV IGBT 6.5 kV IGBT耐压极限的研究
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487953
J. Bauer, O. Schilling, C. Schaeffer, F. Hille
{"title":"Investigations on the ruggedness limit of 6.5 kV IGBT","authors":"J. Bauer, O. Schilling, C. Schaeffer, F. Hille","doi":"10.1109/ISPSD.2005.1487953","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487953","url":null,"abstract":"The save operating area (SOA) of high voltage 6.5 kV IGBTs has been investigated. The ruggedness of the IGBT with planar cell structure is limited by the hole current density in the cell structure arriving from the avalanche generation under turn-off conditions. The impact of current density, V/sub cc/ and vertical IGBT structure on the ruggedness has been taken into account. With a modified cell design the avalanche generation can be reduced significantly. Simulations with a trench IGBT promises additional SOA improvement.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"4 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120836860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A study of correlation between traps and reverse-recovery characteristics of FWDs 圈闭与fwd逆采特征的相关性研究
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487996
T. Sugiyama, S. Yamazaki, S. Nakagaki, M. Ishiko
{"title":"A study of correlation between traps and reverse-recovery characteristics of FWDs","authors":"T. Sugiyama, S. Yamazaki, S. Nakagaki, M. Ishiko","doi":"10.1109/ISPSD.2005.1487996","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487996","url":null,"abstract":"The purpose of this work is to clarify the correlation between traps and reverse-recovery characteristics of freewheeling diodes (FWDs). The traps induced in FWDs have been examined by deep level transient spectroscopy and the reverse-recovery characteristics of FWD with IGBT have been measured and simulated with a trap model. It was found that the difference in the concentration of traps with a shallow and with a deep energy level has a large influence on the reverse-recovery characteristics. Consequently, an increase in the concentration of the charged traps leads to lowering of the peak in voltage generated during reverse-recovery.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125539632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
High Performance Isolated LDMOS with Source Spacer and Asymmetric Hetero-doped Architectures 具有源间隔和非对称杂掺杂结构的高性能隔离LDMOS
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488021
J. Cai, M. Harley-Stead, J. Wołoszyn, S. Park
{"title":"High Performance Isolated LDMOS with Source Spacer and Asymmetric Hetero-doped Architectures","authors":"J. Cai, M. Harley-Stead, J. Wołoszyn, S. Park","doi":"10.1109/ISPSD.2005.1488021","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488021","url":null,"abstract":"A novel isolated LDMOS structure, using a simple yet effective concept of an asymmetric hetero-doped source/drain, is proposed. The asymmetric hetero-doped source/drain reduces the on-state resistance of the transistor due to the high n-type doping used for device drain drift, provides excellent ruggedness for parasitic NPN turned-on due to a minimized n+ source spacer, and also raises the device breakdown voltage due to charge compensation in the composite drain drift region. Therefore, the asymmetric hetero-doped source/drain structure allows the isolated LDMOS to have a high current handling capability with a small device size. Measured results show that a 24 V breakdown voltage new device with a low cost two-layer metal (Al) back-end achieves very low R (sp, on) of 16.6 mOmega.mm2. Furthermore, the new device with 65 V high-side capability achieves good isolation performance even when switching source/drain to -20 V and also gets a cut-off frequency of 13 GHz at a gate voltage of 5.5 V","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121820974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Floating island and thick bottom oxide trench gate MOSFET (FITMOS) - a 60V ultra low on-resistance novel MOSFET with superior internal body diode 浮岛和厚底氧化沟槽栅极MOSFET (FITMOS) -一种60V超低导通电阻的新型MOSFET，具有卓越的内部二极管
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 1900-01-01 DOI: 10.1109/ispsd.2006.1666048
H. Takaya, K. Miyagi, K. Hamada, Y. Okura, N. Tokura, A. Kuroyanagi
{"title":"Floating island and thick bottom oxide trench gate MOSFET (FITMOS) - a 60V ultra low on-resistance novel MOSFET with superior internal body diode","authors":"H. Takaya, K. Miyagi, K. Hamada, Y. Okura, N. Tokura, A. Kuroyanagi","doi":"10.1109/ispsd.2006.1666048","DOIUrl":"https://doi.org/10.1109/ispsd.2006.1666048","url":null,"abstract":"A MOSFET structure named FITMOS has been successfully developed that exhibits record-low loss in the 60 volts breakdown voltage range. The breakdown voltage of 64 volts and specific on-resistance of 22m/spl Omega/mm/sup 2/ (V/sub gs/=15V) this performance exceeds the unipolar limit (Chenming Hu, 1979). The device has a body diode with superior reverse recovery characteristics and exhibits an extremely small value for RonQgd. The distinctive feature of this device is the use of floating islands formed by self-alignment and trench gates with a thick oxide layer on the bottoms. This structure can also be used for the terminal portion of the device, so the increase in the number of fabrication processes is less than 5%. Moreover, the rate of nondefective gates in 3-by-4-mm rectangular devices on an 8-inch wafer is at least 98%.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129766935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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