发布求助
文献互助 智能选刊 最新文献

Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.最新文献

筛选
英文 中文
PDP scan driver with NVDMOS and RESURF PLDMOS 带有NVDMOS和rerefpldmos的PDP扫描驱动程序
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487973
Zhilin Sun, Weifeng Sun, Y. Yi, Chang Chen, W. Yao, Zhenxiong Peng, Longxing Shi
{"title":"PDP scan driver with NVDMOS and RESURF PLDMOS","authors":"Zhilin Sun, Weifeng Sun, Y. Yi, Chang Chen, W. Yao, Zhenxiong Peng, Longxing Shi","doi":"10.1109/ISPSD.2005.1487973","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487973","url":null,"abstract":"A high voltage CMOS IC technology by using 25/spl mu/m thick epitaxy based on 1.2/spl mu/m standard CMOS process has been developed. In this technology, LDMOS and VDMOS are fabricated together. Junction isolation is used to isolate VDMOS from LDMOS, low voltage CMOS, and other VDMOSs. Test results show that the rise time and the fall time of the output stage is about 45ns and 50ns, respectively. For the simplicity of the technology, the cost is saved.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115359407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
4.5 kV 60A SICGT and its Half Bridge Inverter Operation of 20kVA Class 4.5 kV 60A SICGT及其20kVA级半桥逆变器运行
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488009
Y. Sugawara, K. Asano, S. Ogata, A. Agarwal, S. Ryu, J. Palmour, S. Okada, Y. Miyanagi
{"title":"4.5 kV 60A SICGT and its Half Bridge Inverter Operation of 20kVA Class","authors":"Y. Sugawara, K. Asano, S. Ogata, A. Agarwal, S. Ryu, J. Palmour, S. Okada, Y. Miyanagi","doi":"10.1109/ISPSD.2005.1488009","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488009","url":null,"abstract":"4.5kV 60A SICGT of 6mm times 6mm chip size has been developed, which has the largest electric power handling capability among the reported SiC switching devices. Due to the fast turn-on time of 0.08mus and the fast turn-off time of 2.3mus at 250degC, SICGT can realize a low power loss as compared with 4.5kV Si GTOs and 4.5W Si IGBTs. A PWM half bridge inverter was built by using a couple of SICGT modules. Each module consists of one SICGT and two SiC pn diodes in a TO3 type package. The inverter achieved an output power of 20 kVA at V DC of 2kV and carrier frequency of 2kHz, This represents the largest output power among the reported SiC inverters","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128777925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A study of switching-self-clamping-mode "SSCM" as an over-voltage protection feature in high voltage IGBTs 开关自箝位模式“SSCM”作为高压igbt过电压保护功能的研究
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487952
Munaf T. A. Rahimo, A. Kopta, S. Eicher, U. Schlapbach, S. Linder
{"title":"A study of switching-self-clamping-mode \"SSCM\" as an over-voltage protection feature in high voltage IGBTs","authors":"Munaf T. A. Rahimo, A. Kopta, S. Eicher, U. Schlapbach, S. Linder","doi":"10.1109/ISPSD.2005.1487952","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487952","url":null,"abstract":"In this paper, we study the switching-self-clamping-mode \"SSCM\" in high voltage IGBTs in terms of device physics and circuit operation. We present analysis for the HV-IGBT failure mode when operating in SSCM due to an unstable negatively damped system and the design consideration taken into account for avoiding such mode of operation. This enables the introduction of an over-voltage protection feature during device turn-off to add to the existing over-current protection capability under short circuit conditions.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124569348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
High performance superjunction UMOSFETs with split p-columns fabricated by multi-ion-implantations 用多离子注入制备具有拆分p柱的高性能超结umosfet
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487945
Y. Miura, H. Ninomiya, K. Kobayashi
{"title":"High performance superjunction UMOSFETs with split p-columns fabricated by multi-ion-implantations","authors":"Y. Miura, H. Ninomiya, K. Kobayashi","doi":"10.1109/ISPSD.2005.1487945","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487945","url":null,"abstract":"We propose superjunction UMOSFET devices (SJ-UMOS) with split p-column structures for automotive applications with rated voltage of 40-75 V. The split p-column fabricated by multi-ion-implantations consists of p-type islands separated by small distances in an n-type epi-layer. This structure was designed to improve the repetitive inductive switching performance without sacrificing the original benefits of the SJ structure. We achieved a specific on-resistance of 28.7 m/spl Omega/mm/sup 2/ at a gate voltage of 10 V for breakdown voltage of 68.0 V. In addition, we confirmed high immunity against inductive switching stress at 175/spl deg/C and good reverse recovery properties.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"86 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121931914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Ultra High Power 10 kV, 50 A SiC PiN Diodes 超高功率10kv, 50a SiC引脚二极管
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488010
M. Das, B. Hull, J. Richmond, B. Heath, J. Sumakeris, A. Powell
{"title":"Ultra High Power 10 kV, 50 A SiC PiN Diodes","authors":"M. Das, B. Hull, J. Richmond, B. Heath, J. Sumakeris, A. Powell","doi":"10.1109/ISPSD.2005.1488010","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488010","url":null,"abstract":"Ultra high power 10 kV, 50 A SiC PiN diodes have been developed with a low forward voltage drop (VF) of 3.75 V and a fast reverse recovery time of 150 nsec. This is the highest reported power rating for a single SiC chip (dimensions: 8.7 mm times 8.7 mm). Furthermore, all of the historical problems with the SiC PiN diode technology such as ineffective edge termination (VBD increased to > 70% of ideal breakdown voltage), poor ohmic contacts to p-type SiC (rhoc reduced to < 10-4 Omegacm2), and forward voltage drift (DeltaVF reduced to < 0.1 V) have been solved with design, material, and process improvements which have resulted in high overall device yields. A combination of performance, reliability, and yield has the SiC PiN diode technology poised for a revolutionary impact in the world of power semiconductor devices","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134121562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Over 1000V semi-superjunction MOSFET with ultra-low on-resistance below the Si-limit 超过1000V的半超结MOSFET，超低导通电阻低于si极限
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487942
W. Saito, I. Omura, S. Aida, S. Koduki, M. Izumisawa, H. Yoshioka, T. Ogura
{"title":"Over 1000V semi-superjunction MOSFET with ultra-low on-resistance below the Si-limit","authors":"W. Saito, I. Omura, S. Aida, S. Koduki, M. Izumisawa, H. Yoshioka, T. Ogura","doi":"10.1109/ISPSD.2005.1487942","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487942","url":null,"abstract":"Si-MOSFETs with the breakdown voltage of over 1000 V were demonstrated, for the first time, realizing low on-resistance below the theoretical Si-limit. The fabricated MOSFETs have semi-superjunction (SemiSJ) structure, which is the combination of superjunction (SJ) structure and n-bottom assisted layer (BAL). The SemiSJ MOSFETs realize both the high breakdown voltage of 1100 and 1400 V and the low on-resistance of 54 and 163 m/spl Omega/cm/sup 2/, respectively. The fabrication process for the high voltage SemiSJ-MOSFET was completely equivalent to a 600-V class SJ-MOSFET process, which implies that a single optimized process for forming SJ structure for 600 V-class MOSFET can be used for a wide voltage range extending up to 1200 V MOSFET. These results show the possibility of new Si power-MOSFET with higher application voltage range.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134253323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
0.18 μm BCD -High Voltage Gate (HVG) Process to address Advanced Display Drivers Roadmap 0.18 μm BCD -High Voltage Gate (HVG) Process，用于解决高级显示驱动路线图
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488026
M. Annese, S. Bertaiola, G. Croce, A. Milani, R. Roggero, P. Galbiati, C. Contiero
{"title":"0.18 μm BCD -High Voltage Gate (HVG) Process to address Advanced Display Drivers Roadmap","authors":"M. Annese, S. Bertaiola, G. Croce, A. Milani, R. Roggero, P. Galbiati, C. Contiero","doi":"10.1109/ISPSD.2005.1488026","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488026","url":null,"abstract":"This paper describes BCD-HVG8 (High Voltage Gate) process family, a technology optimized to address the small size display driver applications. 20/32/40V devices with thick gate oxide (Vgs max=25V) have been successfully integrated in a 0.18µm BCD platform. Thanks to its flexibility and modularity, the obtained process is suitable to cover the design requirements coming from all of the present different display realization techniques: passive Liquid Crystal Display (LCD), Thin Film Transistors (TFT) or Organic Light Emission Diodes (OLED).","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130856710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A novel drift region self-aligned SOI power MOSFET using a partial exposure technique 一种采用部分曝光技术的新型漂移区自对准SOI功率MOSFET
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487978
L. Guan, J. Sin, Zhibin Xiong, Haitao Liu
{"title":"A novel drift region self-aligned SOI power MOSFET using a partial exposure technique","authors":"L. Guan, J. Sin, Zhibin Xiong, Haitao Liu","doi":"10.1109/ISPSD.2005.1487978","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487978","url":null,"abstract":"In this paper, a novel drift region self-aligned SOI power MOSFET using a partial exposure technique is proposed and demonstrated. The drift region is self-aligned to the channel and was achieved using a simple process without the need of an additional mask. Furthermore, the drift length can be controlled conveniently using different layout designs with a length ranging from 0.3/spl mu/m to a few microns. The fabricated SOI power device has a breakdown voltage of over 20V. Using a 0.7/spl mu/m non-silicide technology, the cutoff frequency (f/sub t/) and maximum oscillation frequency (f/sub max/) of the device are 10.1 GHz and 13.7GHz, respectively.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131141205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Degraded blocking performance of 4H-SiC rectifiers under high dV/dt conditions 高dV/dt条件下4H-SiC整流器阻塞性能下降
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487990
P. Losee, L. Zhu, T. Chow, I. Bhat, R. Gutmann
{"title":"Degraded blocking performance of 4H-SiC rectifiers under high dV/dt conditions","authors":"P. Losee, L. Zhu, T. Chow, I. Bhat, R. Gutmann","doi":"10.1109/ISPSD.2005.1487990","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487990","url":null,"abstract":"We present our pulsed blocking measurements of co-fabricated 4H-SiC Schottky, junction barrier Schottky (JBS), and pin diodes. Schottky diodes fail at pulsed voltages noticeably lower than their static values, while the pulsed leakage currents of JBS and pin diodes (along with commercial SiC rectifiers) remain below our measurable limits until the reverse voltage approaches the static breakdown. From experimental results and numerical simulations, the premature breakdown of the diodes is attributed to the slow response of deep levels associated with dopant implantation, which can leave high field points such as the edge of contacts unprotected under high dV/dt blocking conditions.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133807759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High speed lateral-IGBT with a passive gate 具有无源栅极的高速横向igbt
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487958
T. Terashima, J. Moritani
{"title":"High speed lateral-IGBT with a passive gate","authors":"T. Terashima, J. Moritani","doi":"10.1109/ISPSD.2005.1487958","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487958","url":null,"abstract":"A lateral-IGBT with a passive gate on collector portion has been proposed. Since the collector voltage directly drives the passive gate which controls the parasitic PNPTr, high-speed turn-off is compatible with low on-resistance without a side effect such as snapback I-V characteristics. Simulation results have shown drastic drop of fall time from 120ns to 5ns. Fabricated device have realize 6.8 ohm/mm/sup 2/ @ Kc=2V specific on-resistance, 780V blocking capability and improved turn-off characteristics similar to simulation results.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"234 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114534219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信