A novel drift region self-aligned SOI power MOSFET using a partial exposure technique

In this paper, a novel drift region self-aligned SOI power MOSFET using a partial exposure technique is proposed and demonstrated. The drift region is self-aligned to the channel and was achieved using a simple process without the need of an additional mask. Furthermore, the drift length can be controlled conveniently using different layout designs with a length ranging from 0.3/spl mu/m to a few microns. The fabricated SOI power device has a breakdown voltage of over 20V. Using a 0.7/spl mu/m non-silicide technology, the cutoff frequency (f/sub t/) and maximum oscillation frequency (f/sub max/) of the device are 10.1 GHz and 13.7GHz, respectively.