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Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.最新文献

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Break-through of the trade-off between on-resistance and ESD endurance in LDMOS 突破了LDMOS中导通电阻和ESD耐久性之间的权衡
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487980
N. Suzuki, H. Yamaguchi, S. Shiraki
{"title":"Break-through of the trade-off between on-resistance and ESD endurance in LDMOS","authors":"N. Suzuki, H. Yamaguchi, S. Shiraki","doi":"10.1109/ISPSD.2005.1487980","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487980","url":null,"abstract":"For the purpose of high ESD endurance and low on-resistance in LDMOS, we propose a new trench gate LDMOS. We call this structure HST-LDMOS (hard snapback trench gate LDMOS). In order to improve ESD endurance and on-resistance, the HST-LDMOS has P/sup +/ region between the driftN/sup -/ and N/sup +/ source and trench gate. Simulation results show that the HST-LDMOS achieves the ESD endurance of 16kV/mm/sup 2/ with the specific on-resistance of 6/spl square/6m/spl Omega/ mm/sup 2/. This is the best characteristic ever reported for the trade-off between on-resistance and ESD endurance. Furthermore, we presents the experimental on-resistance and snapback characteristics.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129372507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
1200 V-Class 4H-SiC RESURF MOSFETs with Low On-Resistances 1200个低导通电阻的v级4H-SiC重熔mosfet
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488005
T. Kimoto, H. Kawano, J. Suda
{"title":"1200 V-Class 4H-SiC RESURF MOSFETs with Low On-Resistances","authors":"T. Kimoto, H. Kawano, J. Suda","doi":"10.1109/ISPSD.2005.1488005","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488005","url":null,"abstract":"H-SiC{0001} RESURF MOSFETs with a two-zone structure have been simulated and fabricated. The dose dependencies of experimental breakdown voltage show good agreement with simulation. Through the optimization of implant dose, high-temperature (1700 o C) annealing after ion implantation, and reduction of channel length, a high breakdown voltage of 1330 V and a low on-resistance of 69 m: cm 2 have been obtained. The 4H-SiC(000-1) face is promising for MOS-based devices owing to superior quality of MOS interface, and a performance of 1260 V - 62 m: cm 2 has been achieved. The figure-of-merit (VB 2 /Ron) of the present devices reaches 26 MW/cm 2 , being the best performance among lateral SiC MOSFETs reported.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129824949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Great improvement in turn-on power dissipation of IGBTs with an extra gate charging function 额外的栅极充电功能大大改善了igbt的导通功耗
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487987
Y. Onozawa, M. Otsuki, Y. Seki
{"title":"Great improvement in turn-on power dissipation of IGBTs with an extra gate charging function","authors":"Y. Onozawa, M. Otsuki, Y. Seki","doi":"10.1109/ISPSD.2005.1487987","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487987","url":null,"abstract":"This paper presents a new gate drive circuit using an extra RC-network to realize low turn-on dissipation of IGBTs. The extra capacitance in the gate circuit assists in charging Miller capacitance, therefore the collector voltage tail region during the turn-on period can be reduced drastically without the turn-on dI/sub c//dt increasing. The proposed gate drive method has been achieved 40% reduction in the turn-on switching power dissipation of 1200V-150A IGBT compared with the conventional gate driving.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125499650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Impact of the back gate effect on bipolar junction transistors in smart power SOI technologies 智能功率SOI技术中后门效应对双极结晶体管的影响
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487962
S. Schwantes, M. Graf, V. Dudek
{"title":"Impact of the back gate effect on bipolar junction transistors in smart power SOI technologies","authors":"S. Schwantes, M. Graf, V. Dudek","doi":"10.1109/ISPSD.2005.1487962","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487962","url":null,"abstract":"This work investigates the effect of the back gate electrode on bipolar junction transistors (BJTs) in smart power SOI technologies. The impact on the BJT is discussed by means of measurements and device simulations. It is shown that proper back gate biasing results in a significant performance improvement for either the NPN or the PNP transistor. A design strategy is presented that offers an optimized utilization of the back gate effect.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125581597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Efficient TCAD methodology for ESD failure current prediction of smart power ESD protection 智能电源ESD保护失效电流预测的高效TCAD方法
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487964
C. Salamero, N. Nolhier, M. Bafleur, P. Besse
{"title":"Efficient TCAD methodology for ESD failure current prediction of smart power ESD protection","authors":"C. Salamero, N. Nolhier, M. Bafleur, P. Besse","doi":"10.1109/ISPSD.2005.1487964","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487964","url":null,"abstract":"This work deals with a method to predict ESD protection robustness with TCAD simulations. Tested on different devices and two smart power technologies, the results are validated with electrical measurement and failure analysis. Failure current is always predicted with a good accuracy compared to technology spreading. In addition, the methodology provides a significant simulation time speedup compared to classical methods based on a temperature criterion.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126755769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Integrated Bi-directional Trench Lateral Power MOSFETs for One Chip Lithium-ion Battery Protection ICs 集成双向沟槽横向功率mosfet的单片锂离子电池保护集成电路
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488024
D. H. Lu, N. Fujishima, A. Sugi, M. Sugimoto, S. Matsunaga, M. Sawada, M. Iwaya, K. Takagiwa
{"title":"Integrated Bi-directional Trench Lateral Power MOSFETs for One Chip Lithium-ion Battery Protection ICs","authors":"D. H. Lu, N. Fujishima, A. Sugi, M. Sugimoto, S. Matsunaga, M. Sawada, M. Iwaya, K. Takagiwa","doi":"10.1109/ISPSD.2005.1488024","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488024","url":null,"abstract":"A low specific on-resistance bi-directional trench lateral power MOSFET (BTLPM) has been integrated with a controller in a 0.6mum BiCDMOS process for single-cell lithium-ion battery protector, downsizing the footprint of the protector in chip-scale package to 3mm 2, one-third of its multi-chip counterparts. The first-silicon results of the BTLPM switches demonstrated a breakdown voltage of 22V, a specific on-resistance of 6.8mOmegamm2 at a gate voltage of 4V (a gate electrical field of 2.3MV/cm)","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126872533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
10.3 m/spl Omega/-cm/sup 2/, 2 kV Power DMOSFETs in 4H-SiC 10.3 m/spl ω /-cm/sup 2/， 2 kV功率dmosfet在4H-SiC
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488004
S. Ryu, S. Krishnaswami, M. Das, B. Hull, J. Richmond, B. Heath, A. Agarwal, J. Palmour, J. Scofield
{"title":"10.3 m/spl Omega/-cm/sup 2/, 2 kV Power DMOSFETs in 4H-SiC","authors":"S. Ryu, S. Krishnaswami, M. Das, B. Hull, J. Richmond, B. Heath, A. Agarwal, J. Palmour, J. Scofield","doi":"10.1109/ISPSD.2005.1488004","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488004","url":null,"abstract":"High voltage power DMOSFETs in 4H-SiC are presented in this paper. A 0.5 μm long MOS gate length was used to minimize the MOS channel resistance. The DMOSFETs were able to block 2 kV with gate shorted to the source. At room temperature, a specific on-resistance of 10.3 mΩ-cm was measured with a gate bias of 12 V. The specific on-resistance was reduced to 8 mΩ-cm with 17 V on the gate. At 150 C, the specific on-resistance increased to 14 mΩ-cm with a VGS of 12 V. The increase in drift layer resistance due to a decrease in bulk electron mobility was partly cancelled out by the negative shift in MOS threshold voltage. The device showed substantially lower parasitic capacitance values compared to a typical silicon power MOSFET with a comparable blocking voltage rating, which suggest that this device can offer significant improvement in switching performance over commercially available silicon power MOSFETs.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121184883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A high performance complementary bipolar process controlling base poly-Si over-etching in emitter region and using SOI or PBSOI technique 一种利用SOI或PBSOI技术控制发射极区基极多晶硅过刻的高性能互补双极工艺
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487977
J.H. Kim, S. Lee, H.J. Park, M.H. Choi, D. Wedel, J.J. Kim
{"title":"A high performance complementary bipolar process controlling base poly-Si over-etching in emitter region and using SOI or PBSOI technique","authors":"J.H. Kim, S. Lee, H.J. Park, M.H. Choi, D. Wedel, J.J. Kim","doi":"10.1109/ISPSD.2005.1487977","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487977","url":null,"abstract":"In this paper, for the first time, we suggest a unique complementary bipolar process which is using the 1st base poly-Si in collector interface, and controlling base poly-Si over-etching in emitter region to obtain high voltage and high speed in NPN tr. and PNP tr. concurrently. And we could find out that the peak fr has a lot of variation according to the degree of base poly silicon over etching. We provide a novel high voltage, high speed and latch-up free complementary process fabrication technology using SOI or PBSOI [J.H. Kim], STI (shallow trench isolation) and DTI (deep trench isolation) technology. The biggest strong point is the NPN and PNP transistors have the same values in terms of size and speed. And also, we have solved the crystal defect generated in SOI substrate. The peak fr for NPN and PNP transistors attained 8.0GHz and 8.5GHz, the BVceo for the NPN and PNP devices achieved 15V and 17V, respectively. These values were found to be excellent results as shown in the maximum value of Johnson-limit for the fT-BVceo product in silicon. [Kwok K.Ng] Currently an operational amplifier product, which is higher than competitors in terms of B/W (band width) at same condition, is being developed with this process.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124937159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
56W SiC MESFET transistors with > 50% PAE for L-band applications 具有> 50% PAE的56W SiC MESFET晶体管，用于l波段应用
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487974
B. Luo, P. Chen, A. Higgins, H. Finlay, K. Boutros, B. Pierce, A. Jones, D. Griffey, J. Kolosick
{"title":"56W SiC MESFET transistors with > 50% PAE for L-band applications","authors":"B. Luo, P. Chen, A. Higgins, H. Finlay, K. Boutros, B. Pierce, A. Jones, D. Griffey, J. Kolosick","doi":"10.1109/ISPSD.2005.1487974","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487974","url":null,"abstract":"Packaged 30mm SiC MESFET transistors were demonstrated with peak power density of 1.9W/mm and power-added-efficiency (PAE) of 53%. The target application of these devices is L-band communication. Discrete devices with gate dimension of 2 /spl times/ 400 /spl mu/m show a saturation current density of 320mA/mm and an extrinsic transconductance of 25mS/mm. The cut-off and maximum oscillation frequency of these devices was 12GHz and 17GHz, respectively. Large periphery devices with 10W CW output power rating exhibit stable electrical performance over a period of 1100hrs, with less than /spl plusmn/10% drift in drain-source current under continuous DC stress.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121505327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A method for overvoltage protection of a motor driver IC 一种电机驱动IC过电压保护方法
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487966
F. Trafton, K. Ziemer
{"title":"A method for overvoltage protection of a motor driver IC","authors":"F. Trafton, K. Ziemer","doi":"10.1109/ISPSD.2005.1487966","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487966","url":null,"abstract":"This paper describes a circuit technique that allows semiconductor power devices to be safely used in an IC whose worst-case voltage requirements exceed the breakdown voltages of the power devices. The supply voltage is sensed and the circuit is placed into a non-operational but safe mode of operation (Turtle Mode/spl trade/). Device data is shown for a hard disk drive servo IC implementing this technique.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122590137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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