突破了LDMOS中导通电阻和ESD耐久性之间的权衡

Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI:10.1109/ISPSD.2005.1487980

N. Suzuki, H. Yamaguchi, S. Shiraki

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引用次数: 8

摘要

为了实现高ESD耐久和低导通电阻的目的，我们提出了一种新的沟槽栅LDMOS。我们称这种结构为HST-LDMOS (hard snapback trench gate LDMOS)。为了提高HST-LDMOS的ESD耐久性和导通电阻，HST-LDMOS在漂移N/sup -/和N/sup +/源与沟槽栅极之间设置了P/sup +/区域。仿真结果表明，HST-LDMOS的ESD耐久性为16kV/mm/sup 2/，比导通电阻为6/spl square/6m/spl Omega/ mm/sup 2/。这是迄今为止报道的在导通电阻和ESD耐久性之间权衡的最佳特性。此外，我们给出了实验的导通电阻和回吸特性。

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Break-through of the trade-off between on-resistance and ESD endurance in LDMOS

For the purpose of high ESD endurance and low on-resistance in LDMOS, we propose a new trench gate LDMOS. We call this structure HST-LDMOS (hard snapback trench gate LDMOS). In order to improve ESD endurance and on-resistance, the HST-LDMOS has P/sup +/ region between the driftN/sup -/ and N/sup +/ source and trench gate. Simulation results show that the HST-LDMOS achieves the ESD endurance of 16kV/mm/sup 2/ with the specific on-resistance of 6/spl square/6m/spl Omega/ mm/sup 2/. This is the best characteristic ever reported for the trade-off between on-resistance and ESD endurance. Furthermore, we presents the experimental on-resistance and snapback characteristics.

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Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.

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