Break-through of the trade-off between on-resistance and ESD endurance in LDMOS

Abstract

For the purpose of high ESD endurance and low on-resistance in LDMOS, we propose a new trench gate LDMOS. We call this structure HST-LDMOS (hard snapback trench gate LDMOS). In order to improve ESD endurance and on-resistance, the HST-LDMOS has P/sup +/ region between the driftN/sup -/ and N/sup +/ source and trench gate. Simulation results show that the HST-LDMOS achieves the ESD endurance of 16kV/mm/sup 2/ with the specific on-resistance of 6/spl square/6m/spl Omega/ mm/sup 2/. This is the best characteristic ever reported for the trade-off between on-resistance and ESD endurance. Furthermore, we presents the experimental on-resistance and snapback characteristics.