Impact of the back gate effect on bipolar junction transistors in smart power SOI technologies

Abstract

This work investigates the effect of the back gate electrode on bipolar junction transistors (BJTs) in smart power SOI technologies. The impact on the BJT is discussed by means of measurements and device simulations. It is shown that proper back gate biasing results in a significant performance improvement for either the NPN or the PNP transistor. A design strategy is presented that offers an optimized utilization of the back gate effect.