{"title":"1200 V-Class 4H-SiC RESURF MOSFETs with Low On-Resistances","authors":"T. Kimoto, H. Kawano, J. Suda","doi":"10.1109/ISPSD.2005.1488005","DOIUrl":null,"url":null,"abstract":"H-SiC{0001} RESURF MOSFETs with a two-zone structure have been simulated and fabricated. The dose dependencies of experimental breakdown voltage show good agreement with simulation. Through the optimization of implant dose, high-temperature (1700 o C) annealing after ion implantation, and reduction of channel length, a high breakdown voltage of 1330 V and a low on-resistance of 69 m: cm 2 have been obtained. The 4H-SiC(000-1) face is promising for MOS-based devices owing to superior quality of MOS interface, and a performance of 1260 V - 62 m: cm 2 has been achieved. The figure-of-merit (VB 2 /Ron) of the present devices reaches 26 MW/cm 2 , being the best performance among lateral SiC MOSFETs reported.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2005.1488005","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
H-SiC{0001} RESURF MOSFETs with a two-zone structure have been simulated and fabricated. The dose dependencies of experimental breakdown voltage show good agreement with simulation. Through the optimization of implant dose, high-temperature (1700 o C) annealing after ion implantation, and reduction of channel length, a high breakdown voltage of 1330 V and a low on-resistance of 69 m: cm 2 have been obtained. The 4H-SiC(000-1) face is promising for MOS-based devices owing to superior quality of MOS interface, and a performance of 1260 V - 62 m: cm 2 has been achieved. The figure-of-merit (VB 2 /Ron) of the present devices reaches 26 MW/cm 2 , being the best performance among lateral SiC MOSFETs reported.