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Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.最新文献

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An experimental analysis of localized lifetime and resistivity control by Helium 氦控制局部寿命和电阻率的实验分析
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488000
S. Daliento, L. Mele, P. Spirito, L. Gialanella, M. Romano, B. Limata, R. Carta, L. Bellemo
{"title":"An experimental analysis of localized lifetime and resistivity control by Helium","authors":"S. Daliento, L. Mele, P. Spirito, L. Gialanella, M. Romano, B. Limata, R. Carta, L. Bellemo","doi":"10.1109/ISPSD.2005.1488000","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488000","url":null,"abstract":"In this work we present an experimental study on the effects of helium implantation in silicon. Doses in the range 1 times 1010 - 5 times 1011 atoms/cm2 have been analysed. Results show that, increasing the dose, a saturation effect on the minimum lifetime that can be achieved occurs, while a marked effect on the resistivity of the material appears. The temperature dependence of the resistivity show that changes are due to a trap effect related to an energy level in the bandgap placed at Ec-0.23 eV that is the same of the dominant recombination center induced by helium implantation","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124504371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Cryogenic and high temperature performance of 4H-SiC vertical junction field effect transistors (VJFETs) for space applications 空间应用的4H-SiC垂直结场效应晶体管(vjfet)的低温和高温性能
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487993
L. Cheng, I. Sankin, J. Merrett, V. Bondarenko, R. Kelley, S. Purohit, Y. Koshka, J. Casady, J. Casady, M. Mazzola
{"title":"Cryogenic and high temperature performance of 4H-SiC vertical junction field effect transistors (VJFETs) for space applications","authors":"L. Cheng, I. Sankin, J. Merrett, V. Bondarenko, R. Kelley, S. Purohit, Y. Koshka, J. Casady, J. Casady, M. Mazzola","doi":"10.1109/ISPSD.2005.1487993","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487993","url":null,"abstract":"In this paper, we present an investigation on the different aspects of the performance of a 600V, 3A 4H-SiC vertical-trench junction field effect transistor (VJFET) at cryogenic and high temperatures. Some critical device physics related factors that affect the DC characteristics and switching performance of the device are explored. In particular, the experimental low-temperature performance of 4H-SiC VJFETs (down to 30K or -243/spl deg/C) is presented for the first time to our knowledge.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123664276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
600V SOI gate drive HVIC for medium power applications operating up to 200/spl deg/C 600V SOI栅极驱动HVIC适用于高达200/spl度/C的中功率应用
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487949
S. Pawel, M. Rossberg, R. Herzer
{"title":"600V SOI gate drive HVIC for medium power applications operating up to 200/spl deg/C","authors":"S. Pawel, M. Rossberg, R. Herzer","doi":"10.1109/ISPSD.2005.1487949","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487949","url":null,"abstract":"The design, functionality and measurements of a fully integrated 600V SOI gate drive IC are presented. The seven-channel HVIC is aimed at three-phase systems for low power and medium power applications. Dielectric device isolation and detailed circuit design ensure operation up to a temperature of 200/spl deg/C. Robust signal processing has been given highest attention at all design stages. A dedicated signal reconstruction topology is presented to provide maximum immunity against parasitic coupling from the power plane. The measurements confirming the safe operation of the IC are given.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124632097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
The field charge extraction (FCE) diode: a novel technology for soft recovery high voltage diodes 场电荷提取(FCE)二极管是一种新型的软恢复高压二极管
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487956
A. Kopta, Munaf T. A. Rahimo
{"title":"The field charge extraction (FCE) diode: a novel technology for soft recovery high voltage diodes","authors":"A. Kopta, Munaf T. A. Rahimo","doi":"10.1109/ISPSD.2005.1487956","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487956","url":null,"abstract":"In this paper we present for the first time a newly developed high voltage diode technology, exhibiting soft recovery performance under all operating conditions. The new diode structure is capable of providing the necessary charge for soft recovery behavior by employing the field charge extraction (FCE) technology. Experimental results obtained from initial prototype samples demonstrate a clear breakthrough in soft recovery performance especially for high voltage diodes rated up to 6500V.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129027248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 63
Wafer chip scale packages with efficient power dissipation have small foot-print for portable applications 晶圆片级封装具有高效的功耗，占地面积小，适合便携式应用
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487972
S. Koduri, T. Efland, Q. Mai, M. McKelvie, M. Paugh, D. Robinson
{"title":"Wafer chip scale packages with efficient power dissipation have small foot-print for portable applications","authors":"S. Koduri, T. Efland, Q. Mai, M. McKelvie, M. Paugh, D. Robinson","doi":"10.1109/ISPSD.2005.1487972","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487972","url":null,"abstract":"As personal and portable electronics are becoming more common in our society, we are also expecting these gadgets to be more functional, less expensive, smaller in size, thinner, and lower in weight. All of these conflicting requirements pose additional challenges for the product designers with thermal dissipation issues, and management of heat in the individual components as well as in the overall system. This paper presents state-of-the-art technology in miniature semiconductor packages, wafer chip scale packages (WCSP), and how they are designed to meet several of these contradicting needs.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129172228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Two-stage Hot Carrier Degradation of LDMOS Transistors. LDMOS晶体管的两阶段热载流子退化。
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488016
P. Moens, F. Bauwens, M. Thomason
{"title":"Two-stage Hot Carrier Degradation of LDMOS Transistors.","authors":"P. Moens, F. Bauwens, M. Thomason","doi":"10.1109/ISPSD.2005.1488016","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488016","url":null,"abstract":"This paper analyses the hot carrier behaviour of a lateral n-type DMOS transistor. Variable base charge pumping experiments are performed to locate the different degradation spots in the transistor, as well as to monitor the increase in interface trap density. Upon hot carrier stress, interface traps are formed at three different locations in the device : in the channel, at the source side birds beak, and under the field oxide at the n-well edge. For the degradation of the specific on-resistance Ron, a two-stage degradation is observed, explained and modelled.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129200302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Direct beam lead bonding for trench MOSFET & CSTBT 用于沟槽MOSFET和CSTBT的直接束引线键合
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487954
A. Narazaki, T. Shirasawa, T. Takayama, S. Sudo, S. Hirakawa, N. Asano, K. Ogata, H. Takahashi, T. Minato
{"title":"Direct beam lead bonding for trench MOSFET & CSTBT","authors":"A. Narazaki, T. Shirasawa, T. Takayama, S. Sudo, S. Hirakawa, N. Asano, K. Ogata, H. Takahashi, T. Minato","doi":"10.1109/ISPSD.2005.1487954","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487954","url":null,"abstract":"The next innovation in the power modules has come up with the corroboration between the power chip technology like CSTBT and die packaging technology like the direct transfer mold module, via wireless bonding technology, that is our technology \"direct beam lead bonding (DBLB)\". In this paper, we report the electrical characteristics and the reliabilities of a MOSFET and a CSTBT using DBLB. The DBLB type MOSFETs on-state resistance (R/sub DS(GN)/) can be reduced in 16% comparing with die conventional aluminum (Al) wire bonding type and an avalanche ruggedness (E/sub AVA/) during undamped inductive switching (UIS) is unproved approximately 2 times. It has the excellent reliability under the thermal cycling test between 233K and 398K during over 3000 cycles. Further, the DBLB type CSTBT has, under the short circuit safety operation area (SCSOA) test condition, 11% greater toughness as energy than the Al wiring type.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130669704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A new fault protection circuit of 600V PT-IGBT for the improved avalanche energy employing the floating p-well 采用浮动p井设计了600V PT-IGBT故障保护电路，提高了雪崩能量
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487957
I. Ji, B. Jeon, Young-Hwan Choi, Soo-Seong Kim, M. Han, Yearn-Ik Choi
{"title":"A new fault protection circuit of 600V PT-IGBT for the improved avalanche energy employing the floating p-well","authors":"I. Ji, B. Jeon, Young-Hwan Choi, Soo-Seong Kim, M. Han, Yearn-Ik Choi","doi":"10.1109/ISPSD.2005.1487957","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487957","url":null,"abstract":"A fault protection circuit, which detects over-voltage under short circuit fault, of IGBT for the improved undamped inductive switching (UIS) capability using floating p-well is proposed and fabricated. Experimental results show that the proposed circuit successfully exhibits the reduction of collector current under fault condition when the protection circuit detects the fault signal and immediately lowers gate voltage. We have also verified the operation of the proposed circuit and device by employing the measurement under hard switching fault (HSF) and fault under load (FUL) conditions and two-dimensional mixed-mode simulation.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131249039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Numerical and Experimental Analysis of Single Crystal Diamond Schottky Barrier Diodes 单晶金刚石肖特基势垒二极管的数值与实验分析
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488014
S. J. Rashid, L. Coulbeck, A. Tajani, M. Brezeanu, A. Garraway, T. Butler, N. Rupesinghe, D. Twitchen, G. Amaratunga, Florin Udrea, P. Taylor, M. Dixon, Jan Isberg
{"title":"Numerical and Experimental Analysis of Single Crystal Diamond Schottky Barrier Diodes","authors":"S. J. Rashid, L. Coulbeck, A. Tajani, M. Brezeanu, A. Garraway, T. Butler, N. Rupesinghe, D. Twitchen, G. Amaratunga, Florin Udrea, P. Taylor, M. Dixon, Jan Isberg","doi":"10.1109/ISPSD.2005.1488014","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488014","url":null,"abstract":"We present our findings on the numerical and experimental analysis of diamond Schottky Barrier diodes (SBDs) comprising of intrinsic single crystal (SC) chemical vapour deposited (CVD) diamond layers grown on highly boron doped substrates also grown by CVD. Good correlation with experimental results has been achieved through numerical modelling that has incorporated previously reported data on transport physics and carrier activation. With our numerical model, we are able to match to within 12 to 15% of the measured forward characteristics of fabricated diamond SBDs up to 2 V in excess of the turn on voltage, for two different Schottky metals.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114431479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
The first demonstration of the 1 cm /spl times/ 1 cm SiC thyristor chip 首次演示了1厘米/ 1倍/ 1厘米SiC晶闸管芯片
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487984
A. Agarwal, B. Damsky, J. Richmond, S. Krishnaswami, C. Capell, S. Ryu, J. Palmour
{"title":"The first demonstration of the 1 cm /spl times/ 1 cm SiC thyristor chip","authors":"A. Agarwal, B. Damsky, J. Richmond, S. Krishnaswami, C. Capell, S. Ryu, J. Palmour","doi":"10.1109/ISPSD.2005.1487984","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487984","url":null,"abstract":"We report on the development of the first 1 cm /spl times/ 1 cm SiC thyristor chip capable of handling 1770 V. This demonstrates the present quality of the SiC substrate and epitaxial material. A forward drop of 4 V at 100 A and 200/spl deg/C was measured. The turn-on delay is found to be a strong function of the gate current. At a gate current of 1.5 A, the turn-on delay of 72 ns is observed for anode to cathode current, I/sub AK/=10 A. The turn-on rise time is a strong function of the anode to cathode voltage, V/sub AK/. At V/sub AK/=500 V, the turn-on rise time was 26 ns for I/sub AK/=10 A.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127936477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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