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Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.最新文献

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Modeling the onset of thermal instability in low voltage power MOS: an experimental validation 低电压功率MOS热不稳定性开始的建模:实验验证
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487981
P. Spirito, G. Breglio, V. d’Alessandro
{"title":"Modeling the onset of thermal instability in low voltage power MOS: an experimental validation","authors":"P. Spirito, G. Breglio, V. d’Alessandro","doi":"10.1109/ISPSD.2005.1487981","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487981","url":null,"abstract":"The aim of this work is the validation of a recently proposed analytical model for the prediction of thermal instability in power MOS by means of experimental evidence. The analysis of a number of commercially available devices illustrates the critical role played by some basic electrical parameters on the thermal ruggedness. In particular, it is shown that transistors with large threshold voltage values are more prone to thermally-induced limitations in pulsed safe operating area (SOA).","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124512410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Triple trench gate IGBTs 三槽栅igbt
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487998
S. Berberich, A. Bauer, L. Frey, H. Ryssel
{"title":"Triple trench gate IGBTs","authors":"S. Berberich, A. Bauer, L. Frey, H. Ryssel","doi":"10.1109/ISPSD.2005.1487998","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487998","url":null,"abstract":"In this work, we propose an insulated gate bipolar transistor (IGBT) with a novel lateral triple trench gate architecture, which shows a four times higher forward conduction current compared to devices with a lateral gate or single trench gate structure. For the proof of concept, we realized single trench gate IGBTs using the reduced surface field (RESURF) principle [J.A. Appels, H.M.J. Vaes, A.W. Ludikhuize] for 600V net applications. Typical applications for those integrated smart power systems are, for example, power management of compact fluorescent lamps (CFL) or solid state relays. Further improvement of the forward conduction mode by using triple trench gate structures was studied","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131890924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimized deep trench isolation for high voltage smart power process 针对高压智能电源过程优化的深沟隔离
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487969
R. Lerner, U. Eckoldt, A. Hoelke, Austin Nevin, G. Stoll
{"title":"Optimized deep trench isolation for high voltage smart power process","authors":"R. Lerner, U. Eckoldt, A. Hoelke, Austin Nevin, G. Stoll","doi":"10.1109/ISPSD.2005.1487969","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487969","url":null,"abstract":"This work describes the electrical performance of high voltage deep trench isolation on SOI wafers. Several process and design related effects on the electrical isolation capability are investigated. Several process parameters during the trench process are examined with regard to isolation capability as well as defect generation. Trench edge geometry and layout have also a very strong impact on the isolation capability.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123344218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 600V driver IC with new short protection in hybrid electric vehicle IGBT inverter system 混合动力汽车IGBT逆变系统中具有新型短保护的600V驱动IC
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487950
K. Ishikawa, K. Suda, M. Sasaki, H. Miyazaki
{"title":"A 600V driver IC with new short protection in hybrid electric vehicle IGBT inverter system","authors":"K. Ishikawa, K. Suda, M. Sasaki, H. Miyazaki","doi":"10.1109/ISPSD.2005.1487950","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487950","url":null,"abstract":"We have developed a 600V high voltage half-bridge gate driver IC used to drive large current inverters such as those used in HEVs (hybrid electric vehicles). In order to improve the robustness of short circuit operation, a new short protection circuit and a noise removal circuit were proposed. Furthermore, a reduction of the short circuit current was examined. Thus, this high voltage IC can drive almost all types of IGBT (insulated gate bipolar transistor) modules up to 600A/600V.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"299 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133580417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A Study of MIS - AlGaN/GaN HEMTs with SiO/sub 2/ Films as Gate Insulator 以SiO/ sub2 /薄膜为栅绝缘子的MIS - AlGaN/GaN HEMTs的研究
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488012
M. Sugimoto, M. Kodama, N. Soejima, E. Hayashi, T. Uesugi, T. Kachi
{"title":"A Study of MIS - AlGaN/GaN HEMTs with SiO/sub 2/ Films as Gate Insulator","authors":"M. Sugimoto, M. Kodama, N. Soejima, E. Hayashi, T. Uesugi, T. Kachi","doi":"10.1109/ISPSD.2005.1488012","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488012","url":null,"abstract":"Gate insulator formation methods for GaN based MIS-HEMTs were examined. A SiO2 film formed with the HTO deposition method (HTO film) showed excellent properties. The interface state density of the HTO/GaN structure was 2E11 eV -1 cm -2 and the breakdown field was 8.2 MV/cm. MIS-AlGaN/GaN HEMTs were fabricated using the HTO film. A MIS-HEMT with a gate width of 100Pm was characterized by a maximum drain current of 395 mA/mm and a specific on-resistance of 1.7 m:� cm 2 . A high power MIS-HEMT with a gate width of 31.04 mm showed a maximum drain current of more","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122042281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Cosmic radiation-induced failure mechanism of high voltage IGBT 宇宙辐射诱发高压IGBT失效机理研究
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487985
W. Kaindl, G. Soelkner, H. Schulze, G. Wachutka
{"title":"Cosmic radiation-induced failure mechanism of high voltage IGBT","authors":"W. Kaindl, G. Soelkner, H. Schulze, G. Wachutka","doi":"10.1109/ISPSD.2005.1487985","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487985","url":null,"abstract":"Ionizing radiation-induced current pulses for IGBTs are longer and higher compared to diodes of the same voltage rating. Device simulations based on a recently developed physical model show that this is effected by a current amplification mechanism resulting from the inherent parasitic BJT structures of the IGBT. We investigate whether current amplification also affects the hardness against cosmic radiation by analyzing the failure rates and comparing them with the respective diode.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124717710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A compact model for thin SOI LIGBTs: description, experimental verification and system application 一种轻型SOI灯的紧凑模型:描述、实验验证及系统应用
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487959
E. Napoli, V. Pathirana, F. Udrea, G. Bonnet, T. Trajkovic, G. Amaratunga
{"title":"A compact model for thin SOI LIGBTs: description, experimental verification and system application","authors":"E. Napoli, V. Pathirana, F. Udrea, G. Bonnet, T. Trajkovic, G. Amaratunga","doi":"10.1109/ISPSD.2005.1487959","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487959","url":null,"abstract":"A complete physical model for the lateral IGBT in thin silicon on insulator technology is presented for the first time. The model is oriented to circuit simulators and is implemented in Pspice. Model results are compared against experimental results and Medici numerical simulations. Numerical convergence performance of the model is verified through the simulation of a half bridge circuit and a complete flyback switch mode power supply.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127690097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
ESD robust integrated output device for smart power ICs 用于智能电源集成电路的ESD鲁棒集成输出器件
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1488022
S. Pendharkar, J. Brodsky, P. Hower, R. Steinhoff
{"title":"ESD robust integrated output device for smart power ICs","authors":"S. Pendharkar, J. Brodsky, P. Hower, R. Steinhoff","doi":"10.1109/ISPSD.2005.1488022","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1488022","url":null,"abstract":"An integrated lateral output device is presented which has a very high degree of ESD robustness. The high ESD robustness is achieved with negligible increase in the overall size of the output device. Such an integrated device is ideally suited for high voltage output pins requiring low on-state resistance (Rdson) with stringent system level IEC requirements.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129561159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Hot-carrier reliability of high side NDMOS in smart power SOI technologies 智能功率SOI技术中高侧NDMOS的热载流子可靠性
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487961
F. Dietz, S. Schwantes, T. Stephan, V. Dudek
{"title":"Hot-carrier reliability of high side NDMOS in smart power SOI technologies","authors":"F. Dietz, S. Schwantes, T. Stephan, V. Dudek","doi":"10.1109/ISPSD.2005.1487961","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487961","url":null,"abstract":"The influence of the stacking potential on the hot-carrier (HC) reliability and safe operational area (SOA) of lateral SOI-NDMOS transistors is investigated for the first time. It is shown by measurements and simulation results that a decrease in the off-state breakdown voltage due to the potential of the wafer backside of NDMOS devices does not necessarily implicate a decrease of the HC reliability while the electrical SOA can be reduced.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121440134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A fast and flexible thermal simulation tool validated on smart power devices 一种快速灵活的热模拟工具，在智能电源设备上进行了验证
Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI: 10.1109/ISPSD.2005.1487963
B. Desoete, P. Moens, R. Gillon, E. Driessens, B. Elattari, G. V. D. Bosch, Guido Groeseneken
{"title":"A fast and flexible thermal simulation tool validated on smart power devices","authors":"B. Desoete, P. Moens, R. Gillon, E. Driessens, B. Elattari, G. V. D. Bosch, Guido Groeseneken","doi":"10.1109/ISPSD.2005.1487963","DOIUrl":"https://doi.org/10.1109/ISPSD.2005.1487963","url":null,"abstract":"In this paper we present a thermal simulation tool based on analytical equations, which is able to calculate temperature distributions on a die as a function of time for any number of arbitrary power sources. The tool is much faster than dedicated numerical software and offers a large flexibility to circuit designers. The results have been found to agree well with results from commercial software. Moreover, pulsed DMOS measurements have been performed in order to validate the temperature predictions.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121517937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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