Modeling the onset of thermal instability in low voltage power MOS: an experimental validation

Abstract

The aim of this work is the validation of a recently proposed analytical model for the prediction of thermal instability in power MOS by means of experimental evidence. The analysis of a number of commercially available devices illustrates the critical role played by some basic electrical parameters on the thermal ruggedness. In particular, it is shown that transistors with large threshold voltage values are more prone to thermally-induced limitations in pulsed safe operating area (SOA).