针对高压智能电源过程优化的深沟隔离

Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. Pub Date : 2005-05-23 DOI:10.1109/ISPSD.2005.1487969

R. Lerner, U. Eckoldt, A. Hoelke, Austin Nevin, G. Stoll

{"title":"针对高压智能电源过程优化的深沟隔离","authors":"R. Lerner, U. Eckoldt, A. Hoelke, Austin Nevin, G. Stoll","doi":"10.1109/ISPSD.2005.1487969","DOIUrl":null,"url":null,"abstract":"This work describes the electrical performance of high voltage deep trench isolation on SOI wafers. Several process and design related effects on the electrical isolation capability are investigated. Several process parameters during the trench process are examined with regard to isolation capability as well as defect generation. Trench edge geometry and layout have also a very strong impact on the isolation capability.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"93 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"Optimized deep trench isolation for high voltage smart power process\",\"authors\":\"R. Lerner, U. Eckoldt, A. Hoelke, Austin Nevin, G. Stoll\",\"doi\":\"10.1109/ISPSD.2005.1487969\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work describes the electrical performance of high voltage deep trench isolation on SOI wafers. Several process and design related effects on the electrical isolation capability are investigated. Several process parameters during the trench process are examined with regard to isolation capability as well as defect generation. Trench edge geometry and layout have also a very strong impact on the isolation capability.\",\"PeriodicalId\":154808,\"journal\":{\"name\":\"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.\",\"volume\":\"93 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2005.1487969\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2005.1487969","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 13

摘要

本文描述了SOI晶圆上的高压深沟隔离的电学性能。研究了工艺和设计对电隔离性能的影响。对沟槽工艺中的几个工艺参数进行了隔离性能和缺陷产生的检验。堑壕边缘的几何形状和布局对隔震能力也有很大的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Optimized deep trench isolation for high voltage smart power process

This work describes the electrical performance of high voltage deep trench isolation on SOI wafers. Several process and design related effects on the electrical isolation capability are investigated. Several process parameters during the trench process are examined with regard to isolation capability as well as defect generation. Trench edge geometry and layout have also a very strong impact on the isolation capability.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.

自引率

0.00%

发文量