{"title":"智能功率SOI技术中高侧NDMOS的热载流子可靠性","authors":"F. Dietz, S. Schwantes, T. Stephan, V. Dudek","doi":"10.1109/ISPSD.2005.1487961","DOIUrl":null,"url":null,"abstract":"The influence of the stacking potential on the hot-carrier (HC) reliability and safe operational area (SOA) of lateral SOI-NDMOS transistors is investigated for the first time. It is shown by measurements and simulation results that a decrease in the off-state breakdown voltage due to the potential of the wafer backside of NDMOS devices does not necessarily implicate a decrease of the HC reliability while the electrical SOA can be reduced.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Hot-carrier reliability of high side NDMOS in smart power SOI technologies\",\"authors\":\"F. Dietz, S. Schwantes, T. Stephan, V. Dudek\",\"doi\":\"10.1109/ISPSD.2005.1487961\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The influence of the stacking potential on the hot-carrier (HC) reliability and safe operational area (SOA) of lateral SOI-NDMOS transistors is investigated for the first time. It is shown by measurements and simulation results that a decrease in the off-state breakdown voltage due to the potential of the wafer backside of NDMOS devices does not necessarily implicate a decrease of the HC reliability while the electrical SOA can be reduced.\",\"PeriodicalId\":154808,\"journal\":{\"name\":\"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.\",\"volume\":\"67 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2005.1487961\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2005.1487961","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Hot-carrier reliability of high side NDMOS in smart power SOI technologies
The influence of the stacking potential on the hot-carrier (HC) reliability and safe operational area (SOA) of lateral SOI-NDMOS transistors is investigated for the first time. It is shown by measurements and simulation results that a decrease in the off-state breakdown voltage due to the potential of the wafer backside of NDMOS devices does not necessarily implicate a decrease of the HC reliability while the electrical SOA can be reduced.