{"title":"600V SOI gate drive HVIC for medium power applications operating up to 200/spl deg/C","authors":"S. Pawel, M. Rossberg, R. Herzer","doi":"10.1109/ISPSD.2005.1487949","DOIUrl":null,"url":null,"abstract":"The design, functionality and measurements of a fully integrated 600V SOI gate drive IC are presented. The seven-channel HVIC is aimed at three-phase systems for low power and medium power applications. Dielectric device isolation and detailed circuit design ensure operation up to a temperature of 200/spl deg/C. Robust signal processing has been given highest attention at all design stages. A dedicated signal reconstruction topology is presented to provide maximum immunity against parasitic coupling from the power plane. The measurements confirming the safe operation of the IC are given.","PeriodicalId":154808,"journal":{"name":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","volume":"57 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2005.1487949","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13
Abstract
The design, functionality and measurements of a fully integrated 600V SOI gate drive IC are presented. The seven-channel HVIC is aimed at three-phase systems for low power and medium power applications. Dielectric device isolation and detailed circuit design ensure operation up to a temperature of 200/spl deg/C. Robust signal processing has been given highest attention at all design stages. A dedicated signal reconstruction topology is presented to provide maximum immunity against parasitic coupling from the power plane. The measurements confirming the safe operation of the IC are given.