A high performance complementary bipolar process controlling base poly-Si over-etching in emitter region and using SOI or PBSOI technique

Abstract

In this paper, for the first time, we suggest a unique complementary bipolar process which is using the 1st base poly-Si in collector interface, and controlling base poly-Si over-etching in emitter region to obtain high voltage and high speed in NPN tr. and PNP tr. concurrently. And we could find out that the peak fr has a lot of variation according to the degree of base poly silicon over etching. We provide a novel high voltage, high speed and latch-up free complementary process fabrication technology using SOI or PBSOI [J.H. Kim], STI (shallow trench isolation) and DTI (deep trench isolation) technology. The biggest strong point is the NPN and PNP transistors have the same values in terms of size and speed. And also, we have solved the crystal defect generated in SOI substrate. The peak fr for NPN and PNP transistors attained 8.0GHz and 8.5GHz, the BVceo for the NPN and PNP devices achieved 15V and 17V, respectively. These values were found to be excellent results as shown in the maximum value of Johnson-limit for the fT-BVceo product in silicon. [Kwok K.Ng] Currently an operational amplifier product, which is higher than competitors in terms of B/W (band width) at same condition, is being developed with this process.